R5F21257SNFP#U0 Renesas Electronics America, R5F21257SNFP#U0 Datasheet - Page 402
![IC R8C/25 MCU FLASH 52LQFP](/photos/12/37/123739/r5f21257snfp_u0_sml.jpg)
R5F21257SNFP#U0
Manufacturer Part Number
R5F21257SNFP#U0
Description
IC R8C/25 MCU FLASH 52LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/25r
Specifications of R5F21257SNFP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, Voltage Detect, WDT
Number Of I /o
41
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
52-LQFP
For Use With
R0K521256S000BE - KIT EVAL STARTER FOR R8C/25
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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R8C/24 Group, R8C/25 Group
Rev.3.00
REJ09B0244-0300
18. A/D Converter
The A/D converter consists of one 10-bit successive approximation A/D converter circuit with a capacitive coupling
amplifier. The analog input shares pins P0_0 to P0_7, and P1_0 to P1_3. Therefore, when using these pins, ensure that
the corresponding port direction bits are set to 0 (input mode).
When not using the A/D converter, set the VCUT bit in the ADCON1 register to 0 (Vref unconnected) so that no
current will flow from the VREF pin into the resistor ladder. This helps to reduce the power consumption of the chip.
The result of A/D conversion is stored in the AD register.
Table 18.1 lists the Performance of A/D converter. Figure 18.1 shows a Block Diagram of A/D Converter.
Figures 18.2 and 18.3 show the A/D converter-related registers.
Table 18.1
NOTES:
A/D conversion method
Analog input voltage
Operating clock φAD
Resolution
Absolute accuracy
Operating mode
Analog input pin
A/D conversion start condition
Conversion rate per pin
1. The analog input voltage does not depend on use of a sample and hold function.
2. When 2.7 V ≤ AVCC ≤ 5.5 V, the frequency of φAD must be 10 MHz or below.
3. In repeat mode, only 8-bit mode can be used.
When the analog input voltage is over the reference voltage, the A/D conversion result will be 3FFh
in 10-bit mode and FFh in 8-bit mode.
When 2.2 V ≤ AVCC < 2.7 V, the frequency of φAD must be 5 MHz or below.
Without a sample and hold function, the φAD frequency should be 250 kHz or above.
With a sample and hold function, the φAD frequency should be 1 MHz or above.
Feb 29, 2008
Item
Performance of A/D converter
(1)
(2)
Page 383 of 485
Successive approximation (with capacitive coupling amplifier)
0 V to AVCC
4.2 V ≤ AVCC ≤ 5.5 V
2.2 V ≤ AVCC < 4.2 V
8 bits or 10 bits selectable
AVCC = Vref = 5 V, φAD = 10 MHz
AVCC = Vref = 3.3 V, φAD = 10 MHz
AVCC = Vref = 2.2 V, φAD = 5 MHz
One-shot and repeat
12 pins (AN0 to AN11)
• Software trigger
• Capture
• Without sample and hold function
• With sample and hold function
• 8-bit resolution
• 10-bit resolution ±3 LSB
• 8-bit resolution
• 10-bit resolution ±5 LSB
• 8-bit resolution
• 10-bit resolution ±5 LSB
Set the ADST bit in the ADCON0 register to 1 (A/D conversion starts)
Timer RD interrupt request is generated while the ADST bit is set to 1
8-bit resolution: 49φAD cycles, 10-bit resolution: 59φAD cycles
8-bit resolution: 28φAD cycles, 10-bit resolution: 33φAD cycles
(3)
±2 LSB
±2 LSB
±2 LSB
f1, f2, f4, fOCO-F
f2, f4, fOCO-F
Performance
18. A/D Converter
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