R5F21257SNFP#U0 Renesas Electronics America, R5F21257SNFP#U0 Datasheet - Page 197
![IC R8C/25 MCU FLASH 52LQFP](/photos/12/37/123739/r5f21257snfp_u0_sml.jpg)
R5F21257SNFP#U0
Manufacturer Part Number
R5F21257SNFP#U0
Description
IC R8C/25 MCU FLASH 52LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/25r
Specifications of R5F21257SNFP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, Voltage Detect, WDT
Number Of I /o
41
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
52-LQFP
For Use With
R0K521256S000BE - KIT EVAL STARTER FOR R8C/25
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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R8C/24 Group, R8C/25 Group
Rev.3.00
REJ09B0244-0300
Figure 14.29
Perform the following for the timer mode (input capture and output compare functions).
When using the TRDGRCi (i = 0 or 1) register as the buffer register of the TRDGRAi register
When using the TRDGRDi register as the buffer register of the TRDGRBi register
Bits IMFC and IMFD in the TRDSRi register are set to 1 at the input edge of the TRDIOCi pin when also using
registers TRDGRCi and TRDGRDi as the buffer register in the input capture function.
When also using registers TRDGRCi and TRDGRDi as buffer registers for the output compare function, reset
synchronous PWM mode, complementary PWM mode, and PWM3 mode, bits IMFC and IMFD in the TRDSRi
register are set to 1 by a compare match with the TRDi register.
• Set the IOC3 bit in the TRDIORCi register to 1 (general register or buffer register).
• Set the IOC2 bit in the TRDIORCi register to the same value as the IOA2 bit in the TRDIORAi register.
• Set the IOD3 bit in the TRDIORDi register to 1 (general register or buffer register).
• Set the IOD2 bit in the TRDIORCi register to the same value as the IOB2 bit in the TRDIORAi register.
Feb 29, 2008
i = 0 or 1
The above applies under the following conditions:
• BFCi bit in the TRDMR register is set to 1 (the TRDGRCi register is used as the buffer register of
• Bits IOA2 to IOA0 in the TRDIORAi register are set to 001b (“L” output by the compare match).
the TRDGRAi register).
Buffer Operation in Output Compare Function
TRDGRCi register
TRDGRAi register
TRDIOAi output
TRDGRCi register
TRDi register
(buffer)
Page 178 of 485
(buffer)
m-1
Compare match signal
m
TRDGRAi
register
m
n
Comparator
Transfer
n
m+1
TRDi
14. Timers
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