R5F212A8SNFA#U0 Renesas Electronics America, R5F212A8SNFA#U0 Datasheet - Page 271

• Manufacturer Part Number: R5F212A8SNFA#U0
• Description: IC R8C/2A MCU FLASH 64K 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/2Ar

Specifications of R5F212A8SNFA#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 55
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 64-LQFP
• For Use With: R0K5212D8S001BE - KIT STARTER FOR R8C/2DR0K5212D8S000BE - KIT DEV FOR R8C/2D
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/2A Group, R8C/2B Group
Rev.2.00
REJ09B0324-0200
Table 14.38
i = 0 or 1, j = either A, B, C, or D
Count sources
Count operations
Count period
Count start condition
Count stop condition
Interrupt request generation
timing
TRDIOA0 pin function
TRDIOB0, TRDIOC0,
TRDIOD0, TRDIOA1 to
TRDIOD1 pin functions
INT0 pin function
Read from timer
Write to timer
Select functions
Nov 26, 2007
Item
Input Capture Function Specifications
Page 249 of 580
f1, f2, f4, f8, f32, fOCO40M
External signal input to the TRDCLK pin (valid edge selected by a
program)
Increment
When bits CCLR2 to CCLR0 in the TRDCRi register are set to 000b
(free-running operation).
1/fk × 65536 fk: Frequency of count source
1 (count starts) is written to the TSTARTi bit in the TRDSTR register.
0 (count stops) is written to the TSTARTi bit in the TRDSTR register
when the CSELi bit in the TRDSTR register is set to 1.
• Input capture (valid edge of TRDIOji input or fOCO128 signal edge)
• TRDi register overflows
Programmable I/O port, input-capture input, or TRDCLK (external clock)
input
Programmable I/O port, or input-capture input (selectable by pin)
Programmable I/O port or INT0 interrupt input
The count value can be read by reading the TRDi register.
• When the SYNC bit in the TRDMR register is set to 0 (channels 0 and
• When the SYNC bit in the TRDMR register is set to 1 (channels 0 and
• Input-capture input pin selected
• Input-capture input valid edge selected
• The timing when the TRDi register is set to 0000h
• Buffer operation (Refer to 14.4.2 Buffer Operation.)
• Synchronous operation (Refer to 14.4.3 Synchronous Operation.)
• Digital filter
• Input-capture trigger selected
1 operate independently).
Data can be written to the TRDi register.
1 operate synchronously).
Data can be written to both the TRD0 and TRD1 registers by writing to
the TRDi register.
Either 1 pin or multiple pins among TRDIOAi, TRDIOBi, TRDIOCi, or
TRDIODi.
The rising edge, falling edge, or both the rising and falling edges
At overflow or input capture
The TRDIOji input is sampled, and when the sampled input level match
as 3 times, the level is determined.
fOCO128 can be selected for input-capture trigger input of the
TRDGRA0 register.
Specification
14. Timers