R5F212A8SNFA#U0 Renesas Electronics America, R5F212A8SNFA#U0 Datasheet - Page 425

IC R8C/2A MCU FLASH 64K 64-LQFP

R5F212A8SNFA#U0

Manufacturer Part Number
R5F212A8SNFA#U0
Description
IC R8C/2A MCU FLASH 64K 64-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/2Ar
Datasheets

Specifications of R5F212A8SNFA#U0

Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, PWM, Voltage Detect, WDT
Number Of I /o
55
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
64-LQFP
For Use With
R0K5212D8S001BE - KIT STARTER FOR R8C/2DR0K5212D8S000BE - KIT DEV FOR R8C/2D
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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R8C/2A Group, R8C/2B Group
Rev.2.00
REJ09B0324-0200
Figure 16.9
Figure 16.10
SS Transmit Data Register
SS Receive Data Register
Port Mode Register
b7 b6 b5 b4
b7 b6 b5 b4 b3 b2 b1 b0
NOTE:
b7 b6 b5 b4
1. The SSRDR register retains the data received before an overrun error occurs (ORER bit in the SSSR register set to 1
0 0
(overrun error)). When an overrun error occurs, the receive data may contain errors and therefore should be
discarded.
Nov 26, 2007
b3
b3 b2
0
b2
0
Registers SSTDR and SSRDR
PMR Register
b1
b1
b0
b0
Store the transmit data.
The stored transmit data is transferred to the SSTRSR register and transmission is started
w hen it is detected that the SSTRSR register is empty.
When the next transmit data is w ritten to the SSTDR register during the data transmission from
the SSTRSR register, the data can be transmitted continuously.
When the MLS bit in the SSMR register is set to 1 (transfer data w ith LSB-first), the data in
w hich MSB and LSB are reversed is read, after w riting to the SSTDR register.
Store the receive data.
The receive data is transferred to the SSRDR register and the receive operation is completed
w hen 1 byte of data has been received by the SSTRSR register. At this time, the next receive
operation is possible. Continuous reception is possible using registers SSTRSR and SSRDR.
Bit Symbol
U1PINSEL
INT1SEL
INT2SEL
(b3-b2)
(b6-b5)
Symbol
SSTDR
Symbol
SSRDR
Symbol
IICSEL
PMR
Page 403 of 580
_____
INT1
_____
INT2
Reserved bits
UART1 enable bit
Reserved bits
SSU / I
pin select bit
pin select bit
2
C bus sw itch bit
(1)
Address
Bit Name
Address
Address
00F8h
00BEh
00BFh
Function
Function
0 : Selects P1_5, P1_7
1 : Selects P3_6
0 : Selects P6_6
1 : Selects P3_2
Set to 0.
To use the UART1, set to 1.
Set to 0.
0 : Selects SSU function
1 : Selects I
16. Clock Synchronous Serial Interface
2
C bus function
After Reset
After Reset
After Reset
Function
00h
FFh
FFh
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RO

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