R5F212A8SNFA#U0 Renesas Electronics America, R5F212A8SNFA#U0 Datasheet - Page 487

• Manufacturer Part Number: R5F212A8SNFA#U0
• Description: IC R8C/2A MCU FLASH 64K 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/2Ar

Specifications of R5F212A8SNFA#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 55
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 64-LQFP
• For Use With: R0K5212D8S001BE - KIT STARTER FOR R8C/2DR0K5212D8S000BE - KIT DEV FOR R8C/2D
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/2A Group, R8C/2B Group
Rev.2.00
REJ09B0324-0200
Figure 17.8
Timer RA Set the pulse width measurement level low
Timer RA Set the count source (f1, f2, f8, fOCO)
Timer RA Set the Synch Break width
Hardware LIN Set the LIN operation to stop
Hardware LIN Set to slave mode
Hardware LIN Set the LIN operation to start
Hardware LIN Set the RXD0 input unmasking timing
Hardware LIN Set the register to enable interrupts
Timer RA Set to pulse width measurement mode
Timer RA Set the INT1/TRAIO pin to P1_5
Nov 26, 2007
TEDGSEL bit in the TRAIOC register ← 0
Bits TCK0 to TCK2 in the TRAMR register
TRAPRE register
TRA register
Bits TMOD0 to TMOD2 in the TRAMR register ← 011b
TIOSEL bit in the TRAIOC register ← 1
LINE bit in the LINCR register ← 1
Example of Header Field Reception Flowchart (1)
(After Synch Break detection, or after Synch
Field measurement)
SBE bit in the LINCR register
(Bus collision detection, Synch Break detection,
Synch Field measurement)
Bits BCIE, SBIE, SFIE in the LINCR register
MST bit in the LINCR register ← 0
LINE bit in the LINCR register ← 0
Page 465 of 580
A
For the hardware LIN
function, set the TIOSEL bit
in the TRAIOC register to 1.
Set the count source and registers
TRA and TRAPRE as appropriate
for the Synch Break period.
Select the timing at which to
unmask the RXD0 input for UART0.
If the RXD0 input is chosen to be
unmasked after detection of Synch
Break, the Synch Field signal is
also input to UART0.
17. Hardware LIN