R5F212A8SNFA#U0 Renesas Electronics America, R5F212A8SNFA#U0 Datasheet - Page 286

• Manufacturer Part Number: R5F212A8SNFA#U0
• Description: IC R8C/2A MCU FLASH 64K 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/2Ar

Specifications of R5F212A8SNFA#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 55
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 64-LQFP
• For Use With: R0K5212D8S001BE - KIT STARTER FOR R8C/2DR0K5212D8S000BE - KIT DEV FOR R8C/2D
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/2A Group, R8C/2B Group
Rev.2.00
REJ09B0324-0200
Table 14.40
i = 0 or 1, j = either A, B, C, or D
Count sources
Count operations
Count period
Waveform output timing
Count start condition
Count stop conditions
Interrupt request generation
timing
TRDIOA0 pin function
TRDIOB0, TRDIOC0,
TRDIOD0, TRDIOA1 to
TRDIOD1 pin functions
INT0 pin function
Read from timer
Write to timer
Select functions
Nov 26, 2007
Item
Output Compare Function Specifications
Page 264 of 580
Compare match
Programmable I/O port, pulse output forced cutoff signal input, or INT0 interrupt input
The count value can be read by reading the TRDi register.
• Output-compare output pin selected
f1, f2, f4, f8, f32, fOCO40M
External signal input to the TRDCLK pin (valid edge selected by a program)
Increment
• When bits CCLR2 to CCLR0 in the TRDCRi register are set to 000b (free-running
• Bits CCLR1 to CCLR0 in the TRDCRi register are set to 01b or 10b (set the TRDi
1 (count starts) is written to the TSTARTi bit in the TRDSTR register.
• 0 (count stops) is written to the TSTARTi bit in the TRDSTR register when the
• When the CSELi bit in the TRDSTR register is set to 0, the count stops at the
• Compare match (content of the TRDi register matches content of the TRDGRji
• TRDi register overflows
Programmable I/O port, output-compare output, or TRDCLK (external clock) input
Programmable I/O port or output-compare output (Selectable by pin)
• When the SYNC bit in the TRDMR register is set to 0 (channels 0 and 1 operate
• When the SYNC bit in the TRDMR register is set to 1 (channels 0 and 1 operate
• Output level at the compare match selected
• Initial output level selected
• Timing to set the TRDi register to 0000h
• Buffer operation (Refer to 14.4.2 Buffer Operation.)
• Synchronous operation (Refer to 14.4.3 Synchronous Operation.)
• Output pin in registers TRDGRCi and TRDGRDi changed
• Pulse output forced cutoff signal input (Refer to 14.4.4 Pulse Output Forced
• Timer RD can be used as the internal timer without output.
operation)
1/fk × 65536 fk: Frequency of count source
register to 0000h at the compare match in the TRDGRji register).
Frequency of count source x (n+1)
n: Setting value in the TRDGRji register
CSELi bit in the TRDSTR register is set to 1.
The output compare output pin holds output level before the count stops.
compare match in the TRDGRAi register.
The output compare output pin holds level after output change by the compare
match.
register.)
independently).
Data can be written to the TRDi register.
synchronously).
Data can be written to both the TRD0 and TRD1 registers by writing to the TRDi
register.
Either 1 pin or multiple pins among TRDIOAi, TRDIOBi, TRDIOCi, or TRDIODi.
“L” output, “H” output, or output level inversed
Set the level at period from the count start to the compare match.
Overflow or compare match in the TRDGRAi register
The TRDGRCi register can be used as output control of the TRDIOAi pin and the
TRDGRDi register can be used as output control of the TRDIOBi pin.
Cutoff.)
Specification
14. Timers