MC9S12C128CPBE Freescale Semiconductor, MC9S12C128CPBE Datasheet - Page 135

• Manufacturer Part Number: MC9S12C128CPBE
• Description: IC MCU 128K FLASH 25MHZ 52-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12C128CPBE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Read: Anytime when register is in the map
Write: Anytime when register is in the map
Port A bits 7 through 0 are associated with address lines A15 through A8 respectively and data lines
D15/D7 through D8/D0 respectively. When this port is not used for external addresses such as in single-
chip mode, these pins can be used as general-purpose I/O. Data direction register A (DDRA) determines
the primary direction of each pin. DDRA also determines the source of data for a read of PORTA.
This register is not in the on-chip memory map in expanded and special peripheral modes. Therefore, these
accesses will be echoed externally.
4.3.2.2
Read: Anytime when register is in the map
Write: Anytime when register is in the map
Port B bits 7 through 0 are associated with address lines A7 through A0 respectively and data lines D7
through D0 respectively. When this port is not used for external addresses, such as in single-chip mode,
these pins can be used as general-purpose I/O. Data direction register B (DDRB) determines the primary
direction of each pin. DDRB also determines the source of data for a read of PORTB.
This register is not in the on-chip memory map in expanded and special peripheral modes. Therefore, these
accesses will be echoed externally.
Freescale Semiconductor
Module Base + 0x0001
Starting address location affected by INITRG register setting.
Emulation Narrow with
IVIS, and Peripheral
Expanded Narrow
Expanded Wide,
Single Chip
Port B Data Register (PORTB)
To ensure that you read the value present on the PORTA pins, always wait
at least one cycle after writing to the DDRA register before reading from the
PORTA register.
To ensure that you read the value present on the PORTB pins, always wait
at least one cycle after writing to the DDRB register before reading from the
PORTB register.
Reset
W
R
AB/DB7
Bit 7
PB7
AB7
0
7
Figure 4-3. Port A Data Register (PORTB)
AB/DB6
PB6
AB6
MC9S12C-Family / MC9S12GC-Family
6
0
6
AB/DB5
PB5
AB5
5
0
5
Rev 01.24
NOTE
NOTE
AB/DB4
PB4
AB4
4
4
0
Chapter 4 Multiplexed External Bus Interface (MEBIV3)
AB/DB3
PB3
AB3
3
0
3
AB/DB2
PB2
AB2
2
0
2
AB/DB1
PB1
AB1
1
0
1
AB/DB0
Bit 0
PB0
AB0
0
0
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