R5F21238DFP#U0 Renesas Electronics America, R5F21238DFP#U0 Datasheet - Page 147
![IC R8C/23 MCU FLASH 48-LQFP](/photos/12/38/123822/r5f21238dfp_u0_sml.jpg)
R5F21238DFP#U0
Manufacturer Part Number
R5F21238DFP#U0
Description
IC R8C/23 MCU FLASH 48-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/23r
Specifications of R5F21238DFP#U0
Core Size
16/32-Bit
Program Memory Size
64KB (64K x 8)
Peripherals
POR, Voltage Detect, WDT
Core Processor
R8C
Speed
20MHz
Connectivity
CAN, I²C, LIN, SIO, SSU, UART/USART
Number Of I /o
41
Program Memory Type
FLASH
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
No. Of I/o's
41
Ram Memory Size
3KB
Cpu Speed
20MHz
No. Of Timers
4
Digital Ic Case Style
LQFP
Embedded Interface Type
CAN, I2C, UART
Rohs Compliant
Yes
Cpu Family
R8C
Device Core Size
16b
Frequency (max)
20MHz
Interface Type
I2C/UART
Total Internal Ram Size
3KB
# I/os (max)
41
Number Of Timers - General Purpose
5
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
3V
On-chip Adc
12-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0K521237S000BE - KIT DEV RSK R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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- Download datasheet (6Mb)
R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
Figure 13.3
Watchdog Timer Reset Register
Watchdog Timer Start Register
Count Source Protection Mode Register
b7
NOTES:
b7
b7 b6 b5 b4
NOTES:
1.
2.
1.
2.
0 0 0 0
Do not generate an interrupt betw een 00h and the FFh w ritings.
When the CSPRO bit in the CSPR register is set to 1 (count source protection mode enabled),
0FFFh is set to the w atchdog timer.
When w riting 0 to the CSPROINI bit in the OFS register, the value after reset is set to 10000000b.
Write 0 before w riting 1 to set the CSPRO bit to 1.
0 cannot be set by a program.
b3 b2 b1 b0
0
Registers WDTR, WDTS, and CSPR
0
b0
b0
0
When w riting 00h before w riting FFh, the w atchdog timer is reset.
The default value of the w atchdog timer is set to 7FFFh w hen count source protection
mode is disabled and 0FFFh w hen count source protection mode is enabled.
The w atchdog timer starts counting after a w rite instruction to this register.
Bit Symbol
(b6-b0)
CSPRO
Symbol
Symbol
Symbol
WDTR
WDTS
CSPR
Page 125 of 501
—
Reserved bits
Count source protection mode
select bit
Address
Address
(2)
000Dh
000Eh
Address
Bit Name
001Ch
Function
Function
Set to 0
0 : Count source protection mode disabled
1 : Count source protection mode enabled
Indeterminate
Indeterminate
After Reset
After Reset
After Reset
Function
(1)
00h
(1)
(2)
13. Watchdog Timer
WO
WO
RW
RW
RW
RW
RW
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