R5F21238DFP#U0 Renesas Electronics America, R5F21238DFP#U0 Datasheet - Page 532
![IC R8C/23 MCU FLASH 48-LQFP](/photos/12/38/123822/r5f21238dfp_u0_sml.jpg)
R5F21238DFP#U0
Manufacturer Part Number
R5F21238DFP#U0
Description
IC R8C/23 MCU FLASH 48-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/23r
Specifications of R5F21238DFP#U0
Core Size
16/32-Bit
Program Memory Size
64KB (64K x 8)
Peripherals
POR, Voltage Detect, WDT
Core Processor
R8C
Speed
20MHz
Connectivity
CAN, I²C, LIN, SIO, SSU, UART/USART
Number Of I /o
41
Program Memory Type
FLASH
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
No. Of I/o's
41
Ram Memory Size
3KB
Cpu Speed
20MHz
No. Of Timers
4
Digital Ic Case Style
LQFP
Embedded Interface Type
CAN, I2C, UART
Rohs Compliant
Yes
Cpu Family
R8C
Device Core Size
16b
Frequency (max)
20MHz
Interface Type
I2C/UART
Total Internal Ram Size
3KB
# I/os (max)
41
Number Of Timers - General Purpose
5
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
3V
On-chip Adc
12-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0K521237S000BE - KIT DEV RSK R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Rev.
0.20
REVISION HISTORY
Jun 28, 2006
Date
Page
306
307
309
310
313
315
318
347
348
349
350
351
Figure 16.14 Sample Flowchart of Data Transmission (Clock Synchronous
Communication Mode);
16.2.5.3 Data Reception;
16.2.5.4 Data Transmission/Reception;
16.2.5.4 Data Transmission/Reception, on the 5th line from the bottom;
Figure 16.17 Sample Flowchart of Data Transmission/Reception (Clock
Synchronous Communication Mode) revised.
16.2.6.2 Data Transmission;
16.2.6.2 Data Transmission, on the 9th line from the bottom;
16.2.6.3 Data Reception;
16.2.8 Notes on Clock Synchronous Serial I/O with Chip Select;
Figure 16.46 Example of Register Setting in Master Transmit Mode (I
Bus Interface Mode);
Figure 16.47 Example of Register Setting in Master Receive Mode (I
Bus Interface Mode);
Figure 16.48 Example of Register Setting in Slave Transmit Mode (I
Bus Interface Mode);
Figure 16.49 Example of Register Setting in Slave Receive Mode (I
Bus Interface Mode);
16.3.8 Notes on I
R8C/22 Group, R8C/23 Group Hardware Manual
NOTE revised.
“16.2.5.3 Data Receive” → “16.2.5.3 Data Reception” revised.
“16.2.5.4 Data Transmit/Receive” → “16.2.5.4 Data Transmission/
Reception” revised.
“When setting the ~ transmit is enabled.” deleted.
“16.2.6.2 Data Transmit” → “16.2.6.2 Data Transmission” revised.
“When setting the ~ transmit is enabled.” deleted.
“16.2.6.3 Data Receive” → “16.2.6.3 Data Reception” revised.
“16.2.8 Precautions on Clock Synchronous Serial I/O with Chip Select” →
“16.2.8 Notes on Clock Synchronous Serial I/O with Chip Select” revised.
“Figure 16.46 Example of Register Setting in Master Transmit Mode
(Clock Synchronous Serial)” → “Figure 16.46 Example of Register
Setting in Master Transmit Mode (I
“Figure 16.47 Example of Register Setting in Master Receive Mode
(Clock Synchronous Serial)” → “Figure 16.47 Example of Register
Setting in Master Receive Mode (I
“Figure 16.48 Example of Register Setting in Slave Transmit Mode
(Clock Synchronous Serial)” → “Figure 16.48 Example of Register
Setting in Slave Transmit Mode (I
“Figure 16.49 Example of Register Setting in Slave Receive Mode
(Clock Synchronous Serial)” → “Figure 16.49 Example of Register
Setting in Slave Receive Mode (I
“16.3.8 Precautions on I
Interface” revised.
2
C - 9
O Bus Interface;
2
O Bus Interface” → “16.3.8 Notes on I
Description
Summary
2
2
C Bus Interface Mode)” revised.
2
C Bus Interface Mode)” revised.
2
C Bus Interface Mode)” revised.
C Bus Interface Mode)” revised.
2
O Bus
2
2
C
2
C
2
C
C
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