R5F21238DFP#U0 Renesas Electronics America, R5F21238DFP#U0 Datasheet - Page 326
![IC R8C/23 MCU FLASH 48-LQFP](/photos/12/38/123822/r5f21238dfp_u0_sml.jpg)
R5F21238DFP#U0
Manufacturer Part Number
R5F21238DFP#U0
Description
IC R8C/23 MCU FLASH 48-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/23r
Specifications of R5F21238DFP#U0
Core Size
16/32-Bit
Program Memory Size
64KB (64K x 8)
Peripherals
POR, Voltage Detect, WDT
Core Processor
R8C
Speed
20MHz
Connectivity
CAN, I²C, LIN, SIO, SSU, UART/USART
Number Of I /o
41
Program Memory Type
FLASH
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
No. Of I/o's
41
Ram Memory Size
3KB
Cpu Speed
20MHz
No. Of Timers
4
Digital Ic Case Style
LQFP
Embedded Interface Type
CAN, I2C, UART
Rohs Compliant
Yes
Cpu Family
R8C
Device Core Size
16b
Frequency (max)
20MHz
Interface Type
I2C/UART
Total Internal Ram Size
3KB
# I/os (max)
41
Number Of Timers - General Purpose
5
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
3V
On-chip Adc
12-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0K521237S000BE - KIT DEV RSK R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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- Download datasheet (6Mb)
R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
Figure 16.11
16.2.2
• When SSUMS bit = 0
• When SSUMS bit = 1 (4-wire bus communication
16.2.2.1
(clock synchronous communication mode)
mode), BIDE bit = 0 (standard mode) and MSS bit = 0
(operates as slave device)
The SSTRSR register is the shift register to transmit and receive the serial data.
When the transmit data is transferred from the SSTDR register to the SSTRSR register and the MLS bit in the
SSMR register is set to 0 (MSB-first), the bit 0 in the SSTDR register is transferred to the bit 0 in the SSTRSR
register. When the MLS bit is set to 1 (LSB-first), the bit 7 in the SSTDR register is transferred to the bit 0 in the
SSTRSR register.
Connecting association between the data I/O pin and SSTRSR register (SS shift register) changes according to
a combination of the MSS bit in the SSCRH register and the SSUMS bit in the SSMR2 register. Also,
connecting association changes according to the BIDE bit in the SSMR2 register.
Figure 16.11 shows an Association between Data I/O Pins and SSTRSR Register.
SSTRSR Register
SSTRSR Register
SS Shift Register (SSTRSR)
Association between Data I/O Pins and SS Shift Register
Association between Data I/O Pins and SSTRSR Register
Page 304 of 501
SSO
SSI
SSO
SSI
• When SSUMS bit = 1 (4-wire bus communication mode),
• When SSUMS bit = 1 (4-wire bus communication mode),
BIDE bit = 0 (standard mode) and MSS bit = 1 (operates
as master device)
BIDE bit = 1 (bidirectional mode)
SSTRSR Register
SSTRSR Register
16. Clock Synchronous Serial Interface
SSO
SSI
SSO
SSI
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