R5F21238DFP#U0 Renesas Electronics America, R5F21238DFP#U0 Datasheet - Page 358
![IC R8C/23 MCU FLASH 48-LQFP](/photos/12/38/123822/r5f21238dfp_u0_sml.jpg)
R5F21238DFP#U0
Manufacturer Part Number
R5F21238DFP#U0
Description
IC R8C/23 MCU FLASH 48-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/23r
Specifications of R5F21238DFP#U0
Core Size
16/32-Bit
Program Memory Size
64KB (64K x 8)
Peripherals
POR, Voltage Detect, WDT
Core Processor
R8C
Speed
20MHz
Connectivity
CAN, I²C, LIN, SIO, SSU, UART/USART
Number Of I /o
41
Program Memory Type
FLASH
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
No. Of I/o's
41
Ram Memory Size
3KB
Cpu Speed
20MHz
No. Of Timers
4
Digital Ic Case Style
LQFP
Embedded Interface Type
CAN, I2C, UART
Rohs Compliant
Yes
Cpu Family
R8C
Device Core Size
16b
Frequency (max)
20MHz
Interface Type
I2C/UART
Total Internal Ram Size
3KB
# I/os (max)
41
Number Of Timers - General Purpose
5
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
3V
On-chip Adc
12-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0K521237S000BE - KIT DEV RSK R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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- Download datasheet (6Mb)
R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
Figure 16.33
Figure 16.34
(slave output)
ICSR register
ICSR register
(master output)
(master output)
ICDRS register
ICDRT register
(master output)
(master output)
(slave output)
ICSR register
ICSR register
TDRE bit in
TEND bit in
ICDRS register
ICDRT register
TDRE bit in
TEND bit in
by program
Processing
by program
Processing
SDA
SDA
SDA
SCL
SDA
SCL
Operating Timing in Master Transmit Mode (I
Operating Timing in Master Transmit Mode (I
1
0
1
0
1
0
1
0
(2) Instruction of
(3) Data write to ICDRT
start condition
generation
register
Page 336 of 501
9
A
b7
1
b7
1
b6
(3) Data write to ICDRT
2
register (1st byte)
b6
2
b5
3
b5
Slave address
3
Address + R/W
b4
4
b4
Address + R/W
4
Data n
b3
5
Data n
b3
5
b2
(4) Data write to ICDRT
6
register (2nd byte)
b2
6
b1
7
2
2
C Bus Interface Mode) (1)
C Bus Interface Mode) (2)
b1
7
b0
R/W
8
(6) Generate stop condition and
16. Clock Synchronous Serial Interface
set TEND bit to 0
b0
8
A
9
A/A
9
(7) Set to slave receive mode
(5) Data write to ICDRT
register (3rd byte)
Data 1
Data 1
b7
1
Data 2
b6
2
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