R5F21238DFP#U0 Renesas Electronics America, R5F21238DFP#U0 Datasheet - Page 418
![IC R8C/23 MCU FLASH 48-LQFP](/photos/12/38/123822/r5f21238dfp_u0_sml.jpg)
R5F21238DFP#U0
Manufacturer Part Number
R5F21238DFP#U0
Description
IC R8C/23 MCU FLASH 48-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/23r
Specifications of R5F21238DFP#U0
Core Size
16/32-Bit
Program Memory Size
64KB (64K x 8)
Peripherals
POR, Voltage Detect, WDT
Core Processor
R8C
Speed
20MHz
Connectivity
CAN, I²C, LIN, SIO, SSU, UART/USART
Number Of I /o
41
Program Memory Type
FLASH
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
No. Of I/o's
41
Ram Memory Size
3KB
Cpu Speed
20MHz
No. Of Timers
4
Digital Ic Case Style
LQFP
Embedded Interface Type
CAN, I2C, UART
Rohs Compliant
Yes
Cpu Family
R8C
Device Core Size
16b
Frequency (max)
20MHz
Interface Type
I2C/UART
Total Internal Ram Size
3KB
# I/os (max)
41
Number Of Timers - General Purpose
5
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
3V
On-chip Adc
12-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0K521237S000BE - KIT DEV RSK R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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- Download datasheet (6Mb)
R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
Figure 18.26
Figure 18.27
Figure 18.28
fCAN
CPU read signal
Updating period of
CAN module
CPU reset signal
C0STR register
b8: State_Reset bit
CPU read signal
Updating period of
CAN module
CPU reset signal
C0STR register
b8: State_Reset bit
CPU read signal
Updating period of
the CAN module
CPU reset signal
C0STR register
b8: State_Reset bit
0: CAN operation
1
0: CAN operation
1: CAN reset/initiall-
0: CAN operation
1: CAN reset/initiall-
: CAN reset/initial-
mode
ization mode
mode
ization mode
mode
ization mode
When Polling Period of CPU is 3fCAN or Longer
When Updating Period of CAN Module Matches Access Period from CPU
With a Wait Time of 3fCAN Before CPU Read
Page 396 of 501
Wait time
: Updated without fail in period of 3fCAN
: When the CAN module’s State_Reset bit updating period matches the CPU’s read
: When the CAN module’s State_Reset bit updating period matches the CPU’s read
: Updated without fail in period of 4fCAN
period, it does not enter reset mode, for the CPU read has the higher priority.
period, it does not enter reset mode, for the CPU read has the higher priority.
4fCAN
18. CAN Module
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