R5F21238DFP#U0 Renesas Electronics America, R5F21238DFP#U0 Datasheet - Page 527
![IC R8C/23 MCU FLASH 48-LQFP](/photos/12/38/123822/r5f21238dfp_u0_sml.jpg)
R5F21238DFP#U0
Manufacturer Part Number
R5F21238DFP#U0
Description
IC R8C/23 MCU FLASH 48-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/23r
Specifications of R5F21238DFP#U0
Core Size
16/32-Bit
Program Memory Size
64KB (64K x 8)
Peripherals
POR, Voltage Detect, WDT
Core Processor
R8C
Speed
20MHz
Connectivity
CAN, I²C, LIN, SIO, SSU, UART/USART
Number Of I /o
41
Program Memory Type
FLASH
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
No. Of I/o's
41
Ram Memory Size
3KB
Cpu Speed
20MHz
No. Of Timers
4
Digital Ic Case Style
LQFP
Embedded Interface Type
CAN, I2C, UART
Rohs Compliant
Yes
Cpu Family
R8C
Device Core Size
16b
Frequency (max)
20MHz
Interface Type
I2C/UART
Total Internal Ram Size
3KB
# I/os (max)
41
Number Of Timers - General Purpose
5
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
3V
On-chip Adc
12-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0K521237S000BE - KIT DEV RSK R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Rev.
0.20
REVISION HISTORY
Jun 28, 2006
Date
Page
104
106
118
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127
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129
148
84
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98
10.4.1.3 Low-Speed On-Chip Oscillator Mode, on the 8th line;
10.4.2.2 Entering Wait Mode revised.
10.4.2.3 Pin Status in Wait Mode revised.
10.4.2.4 Exiting Wait Mode revised.
Table 10.3 Interrupts to Exit Wait Mode and Usage Conditions;
Figure 10.10 Time from Wait Mode to Interrupt Routine Execution
added.
Figure 10.12 Procedure for Switching Clock Source from Low-Speed
On-Chip Oscillator to XIN Clock revised.
Figure 10.13 Example of Determining Interrupt Source for Oscillation
Stop Detection, Watchdog Timer, Voltage Monitor 1, or Voltage Monitor
2 Interrupt revised.
10.6 Notes on Clock Generation Circuit revised.
Figure 12.1 Interrupts;
Table 12.2 Relocatable Vector Tables;
Table 12.5 IPL Value When Software or Special Interrupt Is
Acknowledged;
Figure 12.10 Priority Levels of Hardware Interrupts;
12.7 Notes on Interrupts;
Figure 13.1 Block Diagram of Watchdog Timer;
Figure 13.2 Registers OFS and WDC revised.
14. Timers;
Table 14.1 Functional Comparison of Timers;
14.1 Timer RA, the 5th line;
Figure 14.1 Block Diagram of Timer RA revised.
Figure 14.2 Registers TRACR and TRAIOC;
14.1.6 Notes on Timer RA;
R8C/22 Group, R8C/23 Group Hardware Manual
“In this mode, ~ consumption operation.” added.
CM02 = 1 of Timer RA Interrupt revised.
CM02 = 1 of Timer RD Interrupt revised.
Address break (2) added.
“A0RIC” → “S0RIC” corrected.
“Address break” added.
“Address break” added.
“12.7 Precautions on Interrupts” → “12.7 Notes on Interrupts” revised.
“(“L”) active”, “PM12: Bit in PM1 register” added.
“The count source for ~ counting and reloading” deleted.
Count source of Timer RD, “TRCIOA0” → “TRDIOA0” corrected.
“The count source for ~ counting and reloading” added.
The TRAIOC register revised.
“14.1.6 Precautions on Timer RA” → “14.1.6 Notes on Timer RA”
revised.
C - 4
Description
Summary
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