M38513E4FP#U0 Renesas Electronics America, M38513E4FP#U0 Datasheet - Page 20

• Manufacturer Part Number: M38513E4FP#U0
• Description: IC 740 MCU ROM 16K 42SSOP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M38513E4FP#U0

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SIO, UART/USART
• Peripherals: PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: OTP
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 42-SSOP
• Package: 42SSOP
• Family Name: 740
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 34
• Interface Type: I2C-BUS
• On-chip Adc: 5-chx10-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Table 8 Interrupt vector addresses and priority
3851 Group
Notes 1: Vector addresses contain interrupt jump destination addresses.
Rev.1.01
Reset (Note 2)
INT
SCL, SDA
INT
INT
INT
Serial I/O2
I
Timer X
Timer Y
Timer 1
Timer 2
Serial I/O1
reception
Serial I/O1
transmission
CNTR
CNTR
A-D converter
BRK instruction
Interrupt Source
2
C
0
1
2
3
2: Reset function in the same way as an interrupt with the highest priority.
0
1
Oct 15, 2003
(Built-in 24 KB or more ROM)
Priority
10
12
14
15
11
16
17
13
1
2
4
5
6
7
8
9
3
page 18 of 89
Vector Addresses (Note 1)
FFDD
FFFD
FFED
FFFB
FFEF
FFE7
FFE5
FFE3
FFDF
FFF9
FFF7
FFF5
FFF3
FFF1
FFEB
FFE9
FFE1
High
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
FFEC
FFEA
FFDE
FFF6
FFF2
FFEE
FFE8
FFE6
FFE2
FFE0
FFDC
FFFC
FFF0
FFFA
FFF8
FFF4
FFE4
Low
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
At reset
At detection of either rising or
falling edge of INT
At detection of either rising or
falling edge of SCL or SDA input
At detection of either rising or
falling edge of INT
At detection of either rising or
falling edge of INT
At detection of either rising or
falling edge of INT
At completion of serial I/O2 data
reception/transmission
At completion of data transfer
At timer X underflow
At timer Y underflow
At timer 1 underflow
At timer 2 underflow
At completion of serial I/O1 data
reception
At completion of serial I/O1
transfer shift or when transmis-
sion buffer is empty
At detection of either rising or
falling edge of CNTR
At detection of either rising or
falling edge of CNTR
At completion of A-D conversion
At BRK instruction execution
Generating Conditions
Interrupt Request
0
1
2
3
input
input
input
input
0
1
input
input
External interrupt
(active edge selectable)
Switch by Serial I/O2/INT
interrupt source bit
Non-maskable
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
Valid when serial I/O is selected
Non-maskable software interrupt
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
Valid when serial I/O is selected
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
STP release timer underflow
Remarks
3