M38513E4FP#U0 Renesas Electronics America, M38513E4FP#U0 Datasheet - Page 40

• Manufacturer Part Number: M38513E4FP#U0
• Description: IC 740 MCU ROM 16K 42SSOP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M38513E4FP#U0

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SIO, UART/USART
• Peripherals: PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: OTP
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 42-SSOP
• Package: 42SSOP
• Family Name: 740
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 34
• Interface Type: I2C-BUS
• On-chip Adc: 5-chx10-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

3851 Group
Example of Master Transmission
An example of master transmission in the standard clock mode, at
the SCL frequency of 100 kHz and in the ACK return mode is
shown below.
(1) Set a slave address in the high-order 7 bits of the I
(2) Set the ACK return mode and SCL = 100 kHz by setting
(3) Set “00
(4) Set a communication enable status by setting “08
(5) Confirm the bus free condition by the BB flag of the I
(6) Set the address data of the destination of transmission in the
(7) Set “F0
(8) Set transmit data in the I
(9) When transmitting control data of more than 1 byte, repeat
(10) Set “D0
Example of Slave Reception
An example of slave reception in the high-speed clock mode, at
the SCL frequency of 400 kHz, in the ACK non-return mode and
using the addressing format is shown below.
(1) Set a slave address in the high-order 7 bits of the I
(2) Set the no ACK clock mode and SCL = 400 kHz by setting
(3) Set “00
(4) Set a communication enable status by setting “08
(5) When a START condition is received, an address comparison
(6) • When all transmitted addresses are “0” (general call):
(7) Set dummy data in the I
Rev.1.01
• When the transmitted addresses agree with the address set
• In the cases other than the above AD0 and AAS of the I
dress register (address 002C
“85
transmission/reception mode can become initializing condi-
tion.
I
register (address 002D
high-order 7 bits of the I
002B
erate a START condition. At this time, an SCL for 1 byte and
an ACK clock automatically occur.
002B
occur.
step (8).
erate a STOP condition if ACK is not returned from slave
reception side or transmission ends.
dress register (address 002C
“25
transmission/reception mode can become initializing condi-
tion.
I
is performed.
AD0 of the I
and an interrupt request signal occurs.
in (1):
ASS of the I
and an interrupt request signal occurs.
status register (address 002D
rupt request signal occurs.
002B
2
2
C control register (address 002E
C control register (address 002E
16
16
” in the I
16
16
” in the I
16
) and set “0” in the least significant bit.
). At this time, an SCL and an ACK clock automatically
).
16
16
16
16
Oct 15, 2003
” in the I
” in the I
” in the I
” in the I
(Built-in 24 KB or more ROM)
2
2
C status register (address 002D
C status register (address 002D
2
2
C clock control register (address 002F
C clock control register (address 002F
2
2
2
2
C status register (address 002D
C status register (address 002D
C status register (address 002D
C status register (address 002D
16
).
page 38 of 89
2
2
2
C data shift register (address
C data shift register (address
C data shift register (address
16
16
16
) and “0” into the RWB bit.
) and “0” in the RWB bit.
) are set to “0” and no inter-
16
16
).
).
16
16
) is set to “1”
) is set to “1”
16
16
16
16
16
16
2
16
) to gen-
) to gen-
16
) so that
C status
) so that
” in the
” in the
2
2
).
).
C ad-
C ad-
2
C
(8) When receiving control data of more than 1 byte, repeat step
(9) When a STOP condition is detected, the communication
(7).
ends.