M38513E4FP#U0 Renesas Electronics America, M38513E4FP#U0 Datasheet - Page 53

• Manufacturer Part Number: M38513E4FP#U0
• Description: IC 740 MCU ROM 16K 42SSOP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M38513E4FP#U0

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SIO, UART/USART
• Peripherals: PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: OTP
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 42-SSOP
• Package: 42SSOP
• Family Name: 740
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 34
• Interface Type: I2C-BUS
• On-chip Adc: 5-chx10-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

3851 Group
Outline Performance (CPU Rewrite Mode)
CPU rewrite mode is usable in the single-chip or Boot mode. The
only User ROM area can be rewritten in CPU rewrite mode.
In CPU rewrite mode, the CPU erases, programs and reads the in-
ternal flash memory by executing software commands. This
rewrite control program must be transferred to the RAM before it
can be executed.
The MCU enters CPU rewrite mode by applying 5 V ± 0.5 V to the
CNV
1 of address 0FFE
mode is entered.
Use software commands to control program and erase operations.
Whether a program or erase operation has terminated normally or
in error can be verified by reading the status register.
Figure 58 shows the flash memory control register.
Bit 0 is the RY/BY status flag used exclusively to read the operat-
ing status of the flash memory. During programming and erase
operations, it is “0” (busy). Otherwise, it is “1” (ready).
Bit 1 is the CPU Rewrite Mode Select Bit. When this bit is set to
“1”, the MCU enters CPU rewrite mode. Software commands are
accepted once the mode is entered. In CPU rewrite mode, the
CPU becomes unable to access the internal flash memory directly.
Fig. 58 Structure of flash memory control register
Rev.1.01
SS
pin and setting “1” to the CPU Rewrite Mode Select Bit (bit
Oct 15, 2003
b 7
(Built-in 24 KB or more ROM)
N o t e s 1: T h e c o n t e n t s o f f l a s h m e m o r y c o n t r o l r e g i s t e r a r e “ X X X 0 0 0 0 1 ” j u s t a f t e r r e s e t r e l e a s e . I n t h e m a s k
16
). Software commands are accepted once the
2: F o r t h i s b i t t o b e s e t t o “ 1 ” , t h e u s e r n e e d s t o w r i t e “ 0 ” a n d t h e n “ 1 ” t o i t i n s u c c e s s i o n . I f i t i s n o t
3: T h i s b i t i s v a l i d w h e n t h e C P U r e w r i t e m o d e s e l e c t b i t i s “ 1 ” . S e t t h i s b i t 3 t o “ 0 ” s u b s e q u e n t l y a f t e r
4: U s e t h e c o n t r o l p r o g r a m i n t h e a r e a e x c e p t t h e b u i l t - i n f l a s h m e m o r y f o r w r i t e t o t h i s b i t .
R O M v e r s i o n , t h i s a d d r e s s i s r e s e r v e d a r e a .
t h i s p r o c e d u r e , t h i s b i t w i l l n o t b e s e t t o “ 1 ” . A d d i t i o n a l l y , i t i s r e q u i r e d t o e n s u r e t h a t n o i n t e r r u p t
w i l l b e g e n e r a t e d d u r i n g t h a t i n t e r v a l .
U s e t h e c o n t r o l p r o g r a m i n t h e a r e a e x c e p t t h e b u i l t - i n f l a s h m e m o r y f o r w r i t e t o t h i s b i t .
s e t t i n g b i t 3 t o “ 1 ” .
page 51 of 89
b0
F l a s h m e m o r y c o n t r o l r e g i s t e r ( a d d r e s s 0 F F E
F M C R
RY/BY status flag
CPU rewrite mode select bit (Note 2)
CPU rewrite mode entry flag
Flash memory reset bit (Note 3)
User ROM area / Boot ROM area select bit
Reserved bits (Indefinite at read/ “0” at write)
0: Busy (being programmed or erased)
1: Ready
0: Normal mode (Software commands invalid)
1: CPU rewrite mode (Software commands acceptable)
0: Normal mode
1: CPU rewrite mode
0: Normal operation
1: Reset
0: User ROM area accessed
1: Boot ROM area accessed
Therefore, use the control program in the RAM for write to bit 1. To
set this bit to “1”, it is necessary to write “0” and then write “1” in
succession. The bit can be set to “0” by only writing “0”.
Bit 2 is the CPU Rewrite Mode Entry Flag. This flag indicates “1” in
CPU rewrite mode, so that reading this flag can check whether
CPU rewrite mode has been entered or not.
Bit 3 is the flash memory reset bit used to reset the control circuit
of internal flash memory. This bit is used when exiting CPU rewrite
mode and when flash memory access has failed. When the CPU
Rewrite Mode Select Bit is “1”, setting “1” for this bit resets the
control circuit. To set this bit to “1”, it is necessary to write “0” and
then write “1” in succession. To release the reset, it is necessary
to set this bit to “0”.
Bit 4 is the User Area/Boot Area Select Bit. When this bit is set to
“1”, Boot ROM area is accessed, and CPU rewrite mode in Boot
ROM area is available. In Boot mode, this bit is set to “1” auto-
matically. Reprogramming of this bit must be in the RAM.
Figure 59 shows a flowchart for setting/releasing CPU rewrite
mode.
(Note 4)
1 6
) ( N o t e 1 )