M38513E4FP#U0 Renesas Electronics America, M38513E4FP#U0 Datasheet - Page 45

• Manufacturer Part Number: M38513E4FP#U0
• Description: IC 740 MCU ROM 16K 42SSOP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M38513E4FP#U0

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SIO, UART/USART
• Peripherals: PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: OTP
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 42-SSOP
• Package: 42SSOP
• Family Name: 740
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 34
• Interface Type: I2C-BUS
• On-chip Adc: 5-chx10-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

3851 Group
WATCHDOG TIMER
The watchdog timer gives a mean of returning to the reset status
when a program cannot run on a normal loop (for example, be-
cause of a software run-away). The watchdog timer consists of an
8-bit watchdog timer L and an 8-bit watchdog timer H.
Standard Operation of Watchdog Timer
When any data is not written into the watchdog timer control reg-
ister (address 0039
stop state. The watchdog timer starts to count down by writing an
optional value into the watchdog timer control register (address
0039
dog timer H.
Accordingly, programming is usually performed so that writing to
the watchdog timer control register (address 0039
started before an underflow. When the watchdog timer control reg-
ister (address 0039
of the watchdog timer H, STP instruction disable bit, and watch-
dog timer H count source selection bit are read.
At reset or writing to the watchdog timer control register (address
0039
Fig. 47 Block diagram of Watchdog timer
Fig. 48 Structure of Watchdog timer control register
Rev.1.01
Initial value of watchdog timer
16
16
) and an internal reset occurs at an underflow of the watch-
), each watchdog timer H and L are set to “FF
X
CIN
X
IN
Main clock division
ratio selection bits
(Note)
N o t e : A n y o n e o f h i g h - s p e e d , m i d d l e - s p e e d o r l o w - s p e e d m o d e i s s e l e c t e d b y b i t s 7 a n d 6 o f t h e C P U m o d e r e g i s t e r .
Oct 15, 2003
R E S E T
(Built-in 24 KB or more ROM)
16
16
) is read, the values of the high-order 6 bits
) after reset, the watchdog timer is in the
b 7
STP instruction disable bit
page 43 of 89
“ 1 0 ”
“ 0 0 ”
“ 0 1 ”
STP instruction
“FF
watchdog timer
control register is
written to.
1 / 1 6
16
” is set when
W a t c h d o g t i m e r L ( 8 )
16
16
”.
) may be
b 0
Watchdog timer control register
(WDTCON : address 0039
W a t c h d o g t i m e r H ( f o r r e a d - o u t o f h i g h - o r d e r 6 b i t )
S T P i n s t r u c t i o n d i s a b l e b i t
0 : S T P i n s t r u c t i o n e n a b l e d
1 : S T P i n s t r u c t i o n d i s a b l e d
W a t c h d o g t i m e r H c o u n t s o u r c e s e l e c t i o n b i t
0 : W a t c h d o g t i m e r L u n d e r f l o w
1 : f ( X
Bit 7 of the watchdog timer control register (address 0039
mits selecting a watchdog timer H count source. When this bit is
set to “0”, the count source becomes the underflow signal of
watchdog timer L. The detection time is set to 131.072 ms at f(X
= 8 MHz frequency and 32.768 s at f(X
When this bit is set to “1”, the count source becomes the signal di-
vided by 16 for f(X
set to 512 s at f(X
32 kHz frequency. This bit is cleared to “0” after reset.
Bit 6 of the watchdog timer control register (address 0039
mits disabling the STP instruction when the watchdog timer is in
operation.
When this bit is “0”, the STP instruction is enabled.
When this bit is “1”, the STP instruction is disabled, once the STP
instruction is executed, an internal reset occurs. When this bit is
set to “1”, it cannot be rewritten to “0” by program. This bit is
cleared to “0” after reset.
Watchdog timer H count source selection bit operation
Operation of STP instruction disable bit
“0”
“ 1 ”
Watchdog timer H count
source selection bit
I N
) / 1 6 o r f ( X
C I N
W a t c h d o g t i m e r H ( 8 )
) / 1 6
IN
IN
) (or f(X
) = 8 MHz frequency and 128 ms at f(X
R e s e t
c i r c u i t
16
)
CIN
)). The detection time in this case is
CIN
Data bus
) = 32 kHz frequency.
I n t e r n a l r e s e t
“ F F
w a t c h d o g t i m e r
c o n t r o l r e g i s t e r i s
w r i t t e n t o .
1 6
” i s s e t w h e n
16
16
CIN
) per-
) per-
) =
IN
)