DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 174
DF3052BX25V
Manufacturer Part Number
DF3052BX25V
Description
MCU 5V 512K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Specifications of DF3052BX25V
Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF3052BX25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 6 Bus Controller
6.4.3
After driving the BREQ pin low, hold it low until BACK goes low. If BREQ returns to the high
level before BACK goes low, the bus arbiter may operate incorrectly.
To terminate the external-bus-released state, hold the BREQ signal high for at least three states. If
BREQ is high for too short an interval, the bus arbiter may operate incorrectly.
6.4.4
If contention occurs between a transition to software standby mode and a bus request from an
external bus master, the bus may be released for one state just before the transition to software
standby mode (see figure 6.23). When using software standby mode, clear the BRLE bit to 0 in
BRCR before executing the SLEEP instruction.
Rev. 3.00 Mar 21, 2006 page 144 of 814
REJ09B0302-0300
BREQ
BACK
Address bus
Strobe
Figure 6.23 Contention between Bus-Released State and Software Standby Mode
BREQ Input Timing
BREQ
Transition to Software Standby Mode
BREQ
BREQ
Bus-released state
Software standby mode
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