DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 434
DF3052BX25V
Manufacturer Part Number
DF3052BX25V
Description
MCU 5V 512K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Specifications of DF3052BX25V
Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF3052BX25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 11 Programmable Timing Pattern Controller
Different Triggers for TPC Output Groups 0 and 1: If TPC output groups 0 and 1 are triggered
by different compare match events, the address of the upper 4 bits of NDRA (group 1) is H'FFA5
and the address of the lower 4 bits (group 0) is H'FFA7. Bits 3 to 0 of address H'FFA5 and bits 7
to 4 of address H'FFA7 are reserved bits that cannot be modified and are always read as 1.
Address H'FFA5
Bit
Initial value
Read/Write
Address H'FFA7
Bit
Initial value
Read/Write
Rev. 3.00 Mar 21, 2006 page 404 of 814
REJ09B0302-0300
NDR7
R/W
—
—
7
0
7
1
NDR6
Reserved bits
R/W
Next data 7 to 4
These bits store the next output
data for TPC output group 1
—
—
6
0
6
1
NDR5
R/W
—
—
5
0
5
1
NDR4
R/W
—
—
4
0
4
1
NDR3
R/W
—
—
3
1
3
0
Next data 3 to 0
These bits store the next output
data for TPC output group 0
NDR2
Reserved bits
R/W
—
—
2
1
2
0
NDR1
R/W
—
—
1
1
1
0
NDR0
R/W
—
—
0
1
0
0
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