DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 437
DF3052BX25V
Manufacturer Part Number
DF3052BX25V
Description
MCU 5V 512K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Specifications of DF3052BX25V
Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF3052BX25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 437 of 847
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11.2.7
NDERA is an 8-bit readable/writable register that enables or disables TPC output groups 1 and 0
(TP
Bit
Initial value
Read/Write
If a bit is enabled for TPC output by NDERA, then when the ITU compare match event selected in
the TPC output control register (TPCR) occurs, the NDRA value is automatically transferred to
the corresponding PADR bit, updating the output value. If TPC output is disabled, the bit value is
not transferred from NDRA to PADR and the output value does not change.
NDERA is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 0—Next Data Enable 7 to 0 (NDER7 to NDER0): These bits enable or disable TPC
output groups 1 and 0 (TP
Bits 7 to 0:
NDER7 to NDER0
0
1
7
to TP
Next Data Enable Register A (NDERA)
0
) on a bit-by-bit basis.
NDER7
R/W
7
0
Description
TPC outputs TP
(NDR7 to NDR0 are not transferred to PA
TPC outputs TP
(NDR7 to NDR0 are transferred to PA
NDER6
7
R/W
to TP
6
0
0
) on a bit-by-bit basis.
NDER5
R/W
5
0
7
7
to TP
to TP
Next data enable 7 to 0
These bits enable or disable
TPC output groups 1 and 0
NDER4
Section 11 Programmable Timing Pattern Controller
R/W
0
0
4
0
are disabled
are enabled
NDER3
Rev. 3.00 Mar 21, 2006 page 407 of 814
R/W
3
0
7
to PA
NDER2
7
R/W
to PA
2
0
0
)
0
)
NDER1
R/W
1
0
REJ09B0302-0300
(Initial value)
NDER0
R/W
0
0
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