DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 478
DF3052BX25V
Manufacturer Part Number
DF3052BX25V
Description
MCU 5V 512K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Specifications of DF3052BX25V
Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF3052BX25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 13 Serial Communication Interface
13.2.7
SSR is an 8-bit register containing multiprocessor bit values, and status flags that indicate SCI
operating status.
Bit
Initial value
Read/Write
Note:
The CPU can always read and write SSR, but cannot write 1 in the TDRE, RDRF, ORER, PER,
and FER flags. These flags can be cleared to 0 only if they have first been read while set to 1. The
TEND and MPB flags are read-only bits that cannot be written.
Rev. 3.00 Mar 21, 2006 page 448 of 814
REJ09B0302-0300
*
Only 0 can be written, to clear the flag.
Serial Status Register (SSR)
Transmit data register empty
Status flag indicating that transmit data has been transferred from TDR into
TSR and new data can be written in TDR
R/(W)
TDRE
7
1
*
Receive data register full
Status flag indicating that data has been received and stored in RDR
R/(W)
RDRF
6
0
*
Overrun error
Status flag indicating detection of a receive overrun error
ORER
R/(W)
5
0
*
Framing error
Status flag indicating detection of a receive
framing error
R/(W)
FER
4
0
*
Parity error
Status flag indicating detection of
a receive parity error
R/(W)
PER
3
0
*
Transmit end
Status flag indicating end of
transmission
TEND
R
2
1
Multiprocessor bit
Stores the received
multiprocessor bit value
MPB
R
1
0
Multiprocessor
bit transfer
Value of multi-
processor bit to
be transmitted
MPBT
R/W
0
0
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