DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 446
DF3052BX25V
Manufacturer Part Number
DF3052BX25V
Description
MCU 5V 512K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Specifications of DF3052BX25V
Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF3052BX25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 11 Programmable Timing Pattern Controller
Example of Normal TPC Output (Example of Five-Phase Pulse Output): Figure 11.5 shows
an example in which the TPC is used for cyclic five-phase pulse output.
Rev. 3.00 Mar 21, 2006 page 416 of 814
REJ09B0302-0300
1. The ITU channel to be used as the output trigger channel is set up so that GRA is an output compare
2. H'F8 is written in PBDDR and NDERB, and bits G3CMS1, G3CMS0, G2CMS1, and G2CMS0 are set in
3. The timer counter in this ITU channel is started. When compare match A occurs, the NDRB contents are
4. Five-phase overlapping pulse output (one or two phases active at a time) can be obtained by writing H'40,
GRA
H'0000
NDRB
PBDR
TP
TP
TP
TP
TP
TCNT value
register and the counter will be cleared by compare match A. The trigger period is set in GRA. The IMIEA bit
is set to 1 in TIER to enable the compare match A interrupt.
TPCR to select compare match in the ITU channel set up in step 1 as the output trigger. Output data H'80 is
written in NDRB.
transferred to PBDR and output. The compare match/input capture A (IMFA) interrupt service routine writes
the next output data (H'C0) in NDRB.
H'60, H'20, H'30, H'10, H'18, H'08, H'88… at successive IMFA interrupts. If the DMAC is set for activation by
this interrupt, pulse output can be obtained without loading the CPU.
15
14
13
12
11
00
80
Figure 11.5 Normal TPC Output Example (Five-Phase Pulse Output)
80
TCNT
C0
C0
40
40
60
Compare match
60
20
20
30
30
10
10
18
18
08
08
88
88
80
80
C0
C0
40
Time
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