HD6473308RCP10V Renesas Electronics America, HD6473308RCP10V Datasheet - Page 145

• Manufacturer Part Number: HD6473308RCP10V
• Description: MCU 5V 16K,PB-FREE 80-PLCC
• Manufacturer: Renesas Electronics America
• Series: H8® H8/330r

Specifications of HD6473308RCP10V

• Core Size: 8-Bit
• Program Memory Size: 16KB (16K x 8)
• Oscillator Type: Internal
• Core Processor: H8/300
• Speed: 10MHz
• Number Of I /o: 58
• Program Memory Type: OTP
• Ram Size: 512 x 8
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-PLCC
• No. Of I/o's: 58
• Ram Memory Size: 512Byte
• Cpu Speed: 10MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 2
• Digital Ic Case: RoHS Compliant
• Controller Family/series: H8/330
• Peripherals: ADC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply (vcc/vdd): -
• Eeprom Size: -
• Data Converters: -
• Peripherals: -
• Connectivity: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Bit 5
ICICE
Bit 4 – Input Capture Interrupt D Enable (ICIDE): This bit selects whether to request input
capture interrupt D (ICID) when input capture flag D (ICFD) in the timer status/control register
(TCSR) is set to “1.”
Bit 4
ICIDE
Bit 3 – Output Compare Interrupt A Enable (OCIAE): This bit selects whether to request
output compare interrupt A (OCIA) when output compare flag A (OCFA) in the timer status/control
register (TCSR) is set to “1.”
Bit 3
OCIAE
Bit 2 – Output Compare Interrupt B Enable (OCIBE): This bit selects whether to request
output compare interrupt B (OCIB) when output compare flag B (OCFB) in the timer status/control
register (TCSR) is set to “1.”
Bit 2
OCIBE
Bit 1 – Timer overflow Interrupt Enable (OVIE): This bit selects whether to request a free-
running timer overflow interrupt (FOVI) when the timer overflow flag (OVF) in the timer
status/control register (TCSR) is set to “1.”
0
1
0
1
0
1
0
1
Description
Input capture interrupt request C (ICIC) is disabled.
Input capture interrupt request C (ICIC) is enabled.
Description
Input capture interrupt request D (ICID) is disabled.
Input capture interrupt request D (ICID) is enabled.
Description
Output compare interrupt request A (OCIA) is disabled.
Output compare interrupt request A (OCIA) is enabled.
Description
Output compare interrupt request B (OCIB) is disabled.
Output compare interrupt request B (OCIB) is enabled.
130
(Initial value)
(Initial value)
(Initial value)
(Initial value)