HD6473308RCP10V Renesas Electronics America, HD6473308RCP10V Datasheet - Page 243

• Manufacturer Part Number: HD6473308RCP10V
• Description: MCU 5V 16K,PB-FREE 80-PLCC
• Manufacturer: Renesas Electronics America
• Series: H8® H8/330r

Specifications of HD6473308RCP10V

• Core Size: 8-Bit
• Program Memory Size: 16KB (16K x 8)
• Oscillator Type: Internal
• Core Processor: H8/300
• Speed: 10MHz
• Number Of I /o: 58
• Program Memory Type: OTP
• Ram Size: 512 x 8
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-PLCC
• No. Of I/o's: 58
• Ram Memory Size: 512Byte
• Cpu Speed: 10MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 2
• Digital Ic Case: RoHS Compliant
• Controller Family/series: H8/330
• Peripherals: ADC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply (vcc/vdd): -
• Eeprom Size: -
• Data Converters: -
• Peripherals: -
• Connectivity: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

In the bit names that follow, the H8/300 is referred to as the slave and the master CPU as the
master.
Bit 7 – Master Write End Flag (MWEF): This flag bit is used to indicate that the master CPU
has finished writing data in the parallel communication data registers. It is set when the master
CPU writes to PCDR14 and cleared when the H8/300 CPU reads PCDR14.
Bit 7
MWEF
Bit 6 – Enable Master Write Interrupt (EMWI): This bit enables or disables the master write
end interrupt (MWEI).
Bit 6
EMWI
Bit 5 – Slave Write End Flag (SWEF): This flag bit is used to indicate that the H8/300 CPU has
finished writing data in the parallel communication data registers. It is set when the H8/300 CPU
writes to PCDR14 and cleared when the master CPU reads PCDR14.
Bit 5
SWEF
Bit 4 – Enable Acknowledge and Request (EAKAR): This bit enables or disables the RDY
signal output by the H8/330 chip. If enabled:
• The RDY signal goes Low when the H8/300 CPU reads PCDR0 while the dual-port RAM is in
• The RDY signal goes High when the master CPU reads PCDR14 or the PCCSR, or when either
In the non-slave modes this bit has no effect.
0
1
0
1
0
1
the master write mode (MWMF = "1"), or when the H8/300 CPU writes to PCDR14.
the master or H8/300 CPU writes to PCDR0.
Description
The H8/300 CPU has read PCDR14 while the dual-port
RAM was in the master write mode (MWMF = "1").
The master CPU has written data in PCDR14.
Description
The master write end interrupt request (MWEI) is disabled.
The master write end interrupt request (MWEI) is enabled.
Description
The master CPU has read PCDR14.
The H8/300 CPU has written data in PCDR14.
232
(Initial state)
(Initial state)
(Initial state)