HD6473308RCP10V Renesas Electronics America, HD6473308RCP10V Datasheet - Page 97

• Manufacturer Part Number: HD6473308RCP10V
• Description: MCU 5V 16K,PB-FREE 80-PLCC
• Manufacturer: Renesas Electronics America
• Series: H8® H8/330r

Specifications of HD6473308RCP10V

• Core Size: 8-Bit
• Program Memory Size: 16KB (16K x 8)
• Oscillator Type: Internal
• Core Processor: H8/300
• Speed: 10MHz
• Number Of I /o: 58
• Program Memory Type: OTP
• Ram Size: 512 x 8
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-PLCC
• No. Of I/o's: 58
• Ram Memory Size: 512Byte
• Cpu Speed: 10MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 2
• Digital Ic Case: RoHS Compliant
• Controller Family/series: H8/330
• Peripherals: ADC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply (vcc/vdd): -
• Eeprom Size: -
• Data Converters: -
• Peripherals: -
• Connectivity: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pins of port 2 can drive a single TTL load and a 90pF capacitive load when they are used as output
pins. They can also drive light-emitting diodes and a Darlington pair. When they are used as input
pins, they have programmable MOS pull-ups.
Table 5-5 details the port 2 registers.
Table 5-5. Port 2 Registers
Name
Port 2 data direction
register
Port 2 data register
Port 2 Data Direction Register (P2DDR)—H’FFB1
Bit
Mode 1
Modes 2 and 3
P2DDR is an 8-bit register that selects the direction of each pin in port 2. A pin functions as an
output pin if the corresponding bit in P2DDR is set to “1,” and as an input pin if the bit is cleared to
“0.”
Port 2 Data Register (P2DR)—H’FFB3
Bit
Initial value
Read/Write
P2DR is an 8-bit register containing the data for pins P2
output pins it reads the value in the P2DR latch, but for input pins, it obtains the logic level directly
from the pin, bypassing the P2DR latch.
Initial value
Read/Write
Initial value
Read/Write
P2
R/W
7
P2
—
W
DDR P2
7
1
0
7
0
7
Abbreviation
P2DDR
P2DR
R/W
6
P2
—
W
DDR P2
6
1
0
6
0
6
R/W
5
P2
—
W
DDR P2
5
1
0
5
0
5
Read/Write
R/W
W
R/W
82
4
P2
—
W
DDR P2
4
1
0
4
0
4
7
to P2
R/W
Initial value
H’FF (mode 1)
H'00 (modes 2 and 3)
H’00
3
P2
—
W
DDR P2
3
1
0
3
0
3
0
. When the CPU reads P2DR, for
R/W
2
P2
—
W
DDR P2
2
1
0
2
0
2
R/W
1
P2
—
W
DDR P2
1
1
0
1
0
1
Address
H’FFB1
H’FFB3
R/W
0
P2
—
W
DDR
0
1
0
0
0
0