HD6473308RCP10V Renesas Electronics America, HD6473308RCP10V Datasheet - Page 36

• Manufacturer Part Number: HD6473308RCP10V
• Description: MCU 5V 16K,PB-FREE 80-PLCC
• Manufacturer: Renesas Electronics America
• Series: H8® H8/330r

Specifications of HD6473308RCP10V

• Core Size: 8-Bit
• Program Memory Size: 16KB (16K x 8)
• Oscillator Type: Internal
• Core Processor: H8/300
• Speed: 10MHz
• Number Of I /o: 58
• Program Memory Type: OTP
• Ram Size: 512 x 8
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-PLCC
• No. Of I/o's: 58
• Ram Memory Size: 512Byte
• Cpu Speed: 10MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 2
• Digital Ic Case: RoHS Compliant
• Controller Family/series: H8/330
• Peripherals: ADC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply (vcc/vdd): -
• Eeprom Size: -
• Data Converters: -
• Peripherals: -
• Connectivity: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.3 Address Space Map
Figure 2-1 shows a memory map in each of the three operating modes. The on-chip register field
consists of control, status, and data registers for the on-chip supporting modules, I/O ports, and
dual-port RAM.
Off-chip addresses can be accessed only in the expanded modes. Access to an off-chip address in
the single-chip mode does not cause an address error, but all “1” data are returned.
2.3.1 Access Speed
On-chip ROM and RAM are accessed a word (16 bits) at a time in two states. (A “state” is one
system clock period.) The on-chip register field is accessed a byte at a time in three states.
External memory is accessed a byte at a time in three or more states. The basic bus cycle is three
states, but additional wait states can be inserted on request.
2.3.2 IOS
There are two small gaps in the on-chip address space above the on-chip RAM. Addresses H’FF80
to H’FF8F, situated between the on-chip RAM and register field, are off-chip. Addresses H’FFA8
to H’FFAF are also off-chip. These 24 addresses can be conveniently assigned to external I/O
devices.
To simplify the addressing of devices at these addresses, an IOS signal is provided that goes Low
when the CPU accesses addresses H’FF00 to H’FFFF. The IOS signal can be used in place of the
upper 8 bits of the address bus.
19