UPD78F9221CS-CAC-A Renesas Electronics America, UPD78F9221CS-CAC-A Datasheet - Page 197
UPD78F9221CS-CAC-A
Manufacturer Part Number
UPD78F9221CS-CAC-A
Description
MCU 8BIT 2KB FLASH 20PIN
Manufacturer
Renesas Electronics America
Series
78K0S/Kx1+r
Datasheet
1.UPD78F9221MC-5A4-A.pdf
(418 pages)
Specifications of UPD78F9221CS-CAC-A
Core Processor
78K0S
Core Size
8-Bit
Speed
10MHz
Connectivity
LIN, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
15
Program Memory Size
2KB (2K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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(6) Asynchronous serial interface control register 6 (ASICL6)
Address: FF98H After reset: 16H R/W
ASICL6
Note Bit 7 is read-only.
Symbol
This register controls the serial communication operations of serial interface UART6.
ASICL6 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 16H.
Caution ASICL6 can be refreshed (the same value is written) by software during a communication
Figure 11-10. Format of Asynchronous Serial Interface Control Register 6 (ASICL6) (1/2)
operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 are 1 or when bit 7 (POWER6) and
bit 5 (RXE6) of ASIM6 are 1), if 0 data has been written to ASICL6 by SBRT6 and SBTT6.
SBRF6
SBRF6
SBRT6
SBTT6
<7>
0
1
0
1
0
1
If POWER6 = 0 and RXE6 = 0 or if SBF reception has been completed correctly
SBF reception in progress
SBF reception trigger
SBF transmission trigger
SBRT6
<6>
Note
CHAPTER 11 SERIAL INTERFACE UART6
SBTT6
5
User’s Manual U16898EJ6V0UD
SBL62
4
SBF reception status flag
SBF transmission trigger
SBF reception trigger
SBL61
3
SBL60
2
DIR6
1
TXDLV6
0
195
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