UPD78F9221CS-CAC-A Renesas Electronics America, UPD78F9221CS-CAC-A Datasheet - Page 234
UPD78F9221CS-CAC-A
Manufacturer Part Number
UPD78F9221CS-CAC-A
Description
MCU 8BIT 2KB FLASH 20PIN
Manufacturer
Renesas Electronics America
Series
78K0S/Kx1+r
Datasheet
1.UPD78F9221MC-5A4-A.pdf
(418 pages)
Specifications of UPD78F9221CS-CAC-A
Core Processor
78K0S
Core Size
8-Bit
Speed
10MHz
Connectivity
LIN, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
15
Program Memory Size
2KB (2K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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The vector interrupt enable state is set for INTP0, INTP1, and INTTMH1.
(Interrupt priority INTP0 > INTP1 > INTTMH1 (refer to Table12-1))
INTP0 interrupt was first masked.
performed.
12.4.3 Interrupt request pending
execution of the next instruction even if the interrupt request (maskable interrupt and external interrupt) is generated
during the execution. The following shows such instructions (interrupt request pending instruction).
232
In the interrupt INTTMH1 servicing, servicing is performed such that the INTP1 interrupt is given priority, since the
Afterwards, once the interrupt mask for INTP0 is released, INTP0 processing through multiple interrupts is
IE = 0: Interrupt request acknowledgment disabled
Some instructions may keep pending the acknowledgment of an instruction request until the completion of the
Manipulation instruction for interrupt request flag registers (IF0, IF1)
Manipulation instruction for interrupt mask flag registers (MK0, MK1)
INTTMH1
Main processing
Example 3. A priority is controlled by the multiple interrupts
EI
Figure 12-10. Example of Multiple Interrupts (2/2)
IE = 0
CHAPTER 12 INTERRUPT FUNCTIONS
User’s Manual U16898EJ6V0UD
INTP0
INTP1
INTTNH1 servicing
PMK0 = 1
PMK0 = 0
RETI
EI
IE = 0
IE = 0
INTP1 servicing
INTP0 servicing
RETI
RETI
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