UPD78F9221CS-CAC-A Renesas Electronics America, UPD78F9221CS-CAC-A Datasheet - Page 203
UPD78F9221CS-CAC-A
Manufacturer Part Number
UPD78F9221CS-CAC-A
Description
MCU 8BIT 2KB FLASH 20PIN
Manufacturer
Renesas Electronics America
Series
78K0S/Kx1+r
Datasheet
1.UPD78F9221MC-5A4-A.pdf
(418 pages)
Specifications of UPD78F9221CS-CAC-A
Core Processor
78K0S
Core Size
8-Bit
Speed
10MHz
Connectivity
LIN, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
15
Program Memory Size
2KB (2K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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(2) Communication operation
(a) Format and waveform example of normal transmit/receive data
Figures 11-13 and 11-14 show the format and waveform example of the normal transmit/receive data.
1. LSB-first transmission/reception
2. MSB-first transmission/reception
One data frame consists of the following bits.
The character bit length, parity, and stop bit length in one data frame are specified by asynchronous serial
interface operation mode register 6 (ASIM6).
Whether data is communicated with the LSB or MSB first is specified by bit 1 (DIR6) of asynchronous serial
interface control register 6 (ASICL6).
Whether the T
Start bit ... 1 bit
Character bits ... 7 or 8 bits
Parity bit ... Even parity, odd parity, 0 parity, or no parity
Stop bit ... 1 or 2 bits
Start
Start
bit
bit
X
D6 pin outputs normal or inverted data is specified by bit 0 (TXDLV6) of ASICL6.
Figure 11-13. Format of Normal UART Transmit/Receive Data
D0
D7
D1
D6
CHAPTER 11 SERIAL INTERFACE UART6
D2
D5
User’s Manual U16898EJ6V0UD
D3
D4
Character bits
Character bits
1 data frame
1 data frame
D4
D3
D5
D2
D6
D1
D7
D0
Parity
Parity
bit
bit
Stop bit
Stop bit
201
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