UPD78F9221CS-CAC-A Renesas Electronics America, UPD78F9221CS-CAC-A Datasheet - Page 300

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UPD78F9221CS-CAC-A

Manufacturer Part Number
UPD78F9221CS-CAC-A
Description
MCU 8BIT 2KB FLASH 20PIN
Manufacturer
Renesas Electronics America
Series
78K0S/Kx1+r
Datasheet

Specifications of UPD78F9221CS-CAC-A

Core Processor
78K0S
Core Size
8-Bit
Speed
10MHz
Connectivity
LIN, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
15
Program Memory Size
2KB (2K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
<R>
298
Note This setting is not required when the watchdog timer is not used.
Remark
<1> to <12> in Figure 18-20 correspond to <1> to <12> in 18.8.6 (previous page).
The erase command
can be re-executed.
Figure 18-20. Example of Block Erase Operation in Self Programming Mode
<2> Set no. of block to be erased
<7> Clear & restart WDT counter
<8> Execute HALT instruction
<11> Abnormal termination
<4> Set the same value as
<9> Check execution result
that of FLAPH to FLAPHC
the number of executions of
<1> Set erase command
<5> Set FLAPLC to 00H
<3> Set FLAPL to 00H
(WDTE = ACH)
the erase command
CHAPTER 18 FLASH MEMORY
(FLCMD = 03H)
<6> Clear PFS
Block erasure
<10> Check
to FLAPH
User’s Manual U16898EJ6V0UD
The erase command
cannot be re-executed.
Abnormal
Note
<12> Normal termination
Normal

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