UPD78F1201MC-CAB-AX Renesas Electronics America, UPD78F1201MC-CAB-AX Datasheet - Page 117
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UPD78F1201MC-CAB-AX
Manufacturer Part Number
UPD78F1201MC-CAB-AX
Description
MCU 16BIT 78K0R/LX3 30-SSOP
Manufacturer
Renesas Electronics America
Series
78K0R/Ix3r
Datasheet
1.UPD78F1201MC-CAB-AX.pdf
(1067 pages)
Specifications of UPD78F1201MC-CAB-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
40MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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(3) Stack pointer (SP)
(d) Auxiliary carry flag (AC)
(e) In-service priority flags (ISP1, ISP0)
(f) Carry flag (CY)
This is a 16-bit register to hold the start address of the memory stack area. Only the internal RAM area can be
set as the stack area.
The SP is decremented ahead of write (save) to the stack memory and is incremented after read (restored) from
the stack memory.
Each stack operation saves data as shown in Figure 3-13.
Cautions 1. Since reset signal generation makes the SP contents undefined, be sure to initialize the SP
If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all other
cases.
This flag manages the priority of acknowledgeable maskable vectored interrupts. Vectored interrupt requests
specified lower than the value of ISP0 and ISP1 by a priority specification flag register (PRn0L, PRn0H,
PRn1L, PRn1H, PRn2L, PRn2H) (see 17.3 (3)) can not be acknowledged. Actual request acknowledgment
is controlled by the interrupt enable flag (IE).
Remark n = 0, 1
This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out value
upon rotate instruction execution and functions as a bit accumulator during bit operation instruction execution.
2. It is prohibited to use the general-purpose register (FFEE0H to FFEFFH) space as a stack
3. While using the self-programming function, the area of FFE20H to FFEFFH cannot be used
SP SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
before using the stack.
area.
as a stack memory. Furthermore, the areas of FF300H to FF6FFH also cannot be used as
stack memories with the
15
Figure 3-12. Format of Stack Pointer
CHAPTER 3 CPU ARCHITECTURE
μ
User’s Manual U19678EJ1V1UD
PD78F1215, 78F1225, 78F1235, respectively.
0
115
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