UPD78F1201MC-CAB-AX Renesas Electronics America, UPD78F1201MC-CAB-AX Datasheet - Page 311
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UPD78F1201MC-CAB-AX
Manufacturer Part Number
UPD78F1201MC-CAB-AX
Description
MCU 16BIT 78K0R/LX3 30-SSOP
Manufacturer
Renesas Electronics America
Series
78K0R/Ix3r
Datasheet
1.UPD78F1201MC-CAB-AX.pdf
(1067 pages)
Specifications of UPD78F1201MC-CAB-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
40MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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6.5 Channel Output (TOn pin) Control
6.5.1 TOn pin output circuit configuration ( When the INVERTER CONTROL FUNCTIONS is not used)
Interrupt signal of the master channel
Interrupt signal of the slave channel
The following describes the TOn pin output circuit.
<1> When TOMn = 0 (master channel output mode), the set value of the TOL0 register is ignored and only
<2> When TOMn = 1 (slave channel output mode), both INTTMn (master channel timer interrupt) and INTTMp
<3> While timer output is enabled (TOEn = 1), INTTMn (master channel timer interrupt) and INTTMp (slave
<4> While timer output is disabled (TOEn = 0), writing to TOn bit to the target channel (TOn write signal)
<5> The TOn register can always be read, and the TOn pin output level can be checked.
Remark
INTTMp (slave channel timer interrupt) is transmitted to the TO0 register.
(slave channel timer interrupt) are transmitted to the TO0 register.
At this time, the TOL0 register becomes valid and the signals are controlled as follows:
When INTTMn and INTTMp are simultaneously generated, (0% output of PWM), INTTMp (reset signal)
takes priority, and INTTMn (set signal) is masked.
channel timer interrupt) are transmitted to the TOn. Writing to the TO0 register (TOn write signal)
becomes invalid.
When TOEn = 1, the TOn pin output never changes with signals other than interrupt signals.
To initialize the TOn pin output level, it is necessary to set the timer operation is stopped (TOEn = 0) and
to write a value to TOn.
becomes valid. When timer output is disabled (TOEn = 0), neither INTTMn (master channel timer
interrupt) nor INTTMp (slave channel timer interrupt) is transmitted to TO0 register.
When TOLn = 0: Forward operation (INTTMn → set, INTTMp → reset)
When TOLn = 1: Reverse operation (INTTMn → reset, INTTMp → set)
n: Channel number, p: Slave channel number
n = 00 to 11 (n = 00, 02, 04, 06, 08, 10 for master channel. n = 02 to 07 and 09: Timer input pin
(TIn) of 78K0R/IB3. n = 02 to 07 and 11: Timer output pin (TOn) of 78K0R/IB3.)
n < p ≤ 11 (For details of the relation between the master channel and slave channel, refer to 6.4
Basic Rules of Simultaneous Channel Operation Function.)
(INTTMn)
(INTTMp)
Figure 6-25. Output Circuit Configuration
CHAPTER 6 TIMER ARRAY UNIT TAUS
User’s Manual U19678EJ1V1UD
<1>
<2>
TOLn
TOMn
TOEn
<3>
TOn write signal
<4>
TOn register
Set
Reset/toggle
<5>
Internal bus
TOn pin
309
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