UPD78F1201MC-CAB-AX Renesas Electronics America, UPD78F1201MC-CAB-AX Datasheet - Page 933
![no-image](/images/manufacturer_photos/0/5/560/renesas_electronics_america_sml.jpg)
UPD78F1201MC-CAB-AX
Manufacturer Part Number
UPD78F1201MC-CAB-AX
Description
MCU 16BIT 78K0R/LX3 30-SSOP
Manufacturer
Renesas Electronics America
Series
78K0R/Ix3r
Datasheet
1.UPD78F1201MC-CAB-AX.pdf
(1067 pages)
Specifications of UPD78F1201MC-CAB-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
40MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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(3) Port mode register 12 (PM12)
When using the P120/EXLVI/INTP0 pin for external low-voltage detection potential input, set PM120 to 1. At this
time, the output latch of P120 may be 0 or 1.
PM12 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to FFH.
Address: FFF2CH
Symbol
PM12
Cautions 2. Change the LVIS value with either of the following methods.
PM120
7
1
0
1
3. When an input voltage from the external input pin (EXLVI) is detected, the detection
4. To read LVIS after writing this register, secure the time of one or more clock.
voltage (V
• When changing the value after stopping LVI
• When changing the value after setting to the mode used as an interrupt (LVIMD =
After reset: FFH
0)
Output mode (output buffer on)
Input mode (output buffer off)
Figure 21-4. Format of Port Mode Register 12 (PM12)
<1> Stop LVI (LVION = 0).
<2> Change the LVIS register.
<3> Set to the mode used as an interrupt (LVIMD = 0).
<4> Mask LVI interrupts (LVIMK = 1).
<5> Enable LVI operation (LVION = 1).
<6> Before cancelling the LVI interrupt mask (LVIMK = 0), clear it with software
<1> Mask LVI interrupts (LVIMK = 1).
<2> Set to the mode used as an interrupt (LVIMD = 0).
<3> Change the LVIS register.
<4> Before cancelling the LVI interrupt mask (LVIMK = 0), clear it with software
6
1
because an LVIIF flag may be set when LVI operation is enabled.
because an LVIIF flag may be set when the LVIS register is changed.
EXLVI
CHAPTER 21 LOW-VOLTAGE DETECTOR
) is fixed. Therefore, setting of LVIS is not necessary.
R/W
5
1
User’s Manual U19678EJ1V1UD
P120 pin I/O mode selection
4
1
3
1
2
1
1
1
PM120
0
931
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