UPD78F1201MC-CAB-AX Renesas Electronics America, UPD78F1201MC-CAB-AX Datasheet - Page 360
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UPD78F1201MC-CAB-AX
Manufacturer Part Number
UPD78F1201MC-CAB-AX
Description
MCU 16BIT 78K0R/LX3 30-SSOP
Manufacturer
Renesas Electronics America
Series
78K0R/Ix3r
Datasheet
1.UPD78F1201MC-CAB-AX.pdf
(1067 pages)
Specifications of UPD78F1201MC-CAB-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
40MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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358
TAUS
default
setting
Channel
default
setting
Remark
Figure 6-70. Operation Procedure When Multiple PWM Output Function Is Used (Output Two Types of
Sets the TAU0EN bit of the PER2 register to 1.
Sets the TPS0 register.
Sets the TMRn, TMRp, and TMRq registers of each
channel to be used (determines operation mode of
channels).
An interval (period) value is set to the TDRn register of
the master channel, and a duty factor is set to the TDRp
and TDRq registers of the slave channel.
Sets slave channel.
n = 00, 02, 04, 06, 08, 10
n < p < q ≤ 11
However, p and q are consecutive integers.
Determines the clock frequencies of CK00 and CK01
for channels 0 to 7, and those of CK02 and CK03 for
channels 8 to 11.
The TOMp and TOMq bits of the TOM0 register is set
to 1 (slave channel output mode).
Clears the TOLp and TOLq bits to 0.
Sets the TOp and TOq bits and determines default
level of the TOp and TOq outputs.
Sets TOEp or TOEq to 1 and enables operation of
TOp or TOq.
Clears the port register and port mode register to 0.
Software Operation
CHAPTER 6 TIMER ARRAY UNIT TAUS
User’s Manual U19678EJ1V1UD
PWMs) (1/2)
Power-off status
Power-on status. Each channel stops operating.
Channel stops operating.
(Clock is supplied and some power is consumed.)
The TOp and TOq pins go into Hi-Z output state.
The TOp and TOq default setting levels are output when
the port mode register is in output mode and the port
register is 0.
TOp or TOq does not change because channel stops
operating.
The TOp and TOq pins output the TOp and TOq set levels.
(Clock supply is stopped and writing to each register is
disabled.)
(Clock supply is started and writing to each register is
enabled.)
Hardware Status
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