SAK-XE167GM-72F80L AA Infineon Technologies, SAK-XE167GM-72F80L AA Datasheet - Page 49
SAK-XE167GM-72F80L AA
Manufacturer Part Number
SAK-XE167GM-72F80L AA
Description
IC MCU 16BIT FLASH 144-LQFP
Manufacturer
Infineon Technologies
Series
XE16xr
Datasheet
1.SAF-XE167KM-48F80L_AA.pdf
(140 pages)
Specifications of SAK-XE167GM-72F80L AA
Core Processor
C166SV2
Core Size
16-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, I²C, LIN, SPI, SSC, UART/USART, USI
Peripherals
I²S, POR, PWM, WDT
Number Of I /o
119
Program Memory Size
576KB (576K x 8)
Program Memory Type
FLASH
Ram Size
50K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
144-LFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
SP000628642
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3
The architecture of the XE167xM combines advantages of RISC, CISC, and DSP
processors with an advanced peripheral subsystem in a well-balanced design. On-chip
memory blocks allow the design of compact systems-on-silicon with maximum
performance suited for computing, control, and communication.
The on-chip memory blocks (program code memory and SRAM, dual-port RAM, data
SRAM) and the generic peripherals are connected to the CPU by separate high-speed
buses. Another bus, the LXBus, connects additional on-chip resources and external
resources (see
enabling the concurrent operation of several subsystems of the XE167xM.
The block diagram gives an overview of the on-chip components and the advanced
internal bus structure of the XE167xM.
Figure 3
Data Sheet
ADC1
10-Bit
Control, StandBy RAM
8-Bit
System Functions
Clock, Reset, Power
Flash Memory
Functional Description
PSRAM
Block Diagram
ADC0
10-Bit
8-Bit
Figure
BRGen
GPT
T2
T3
T4
T5
T6
3). This bus structure enhances overall system performance by
Analog and Digital General Purpose IO (GPIO) Ports
CC2
T7
T8
MPU
CCU6x
DPRAM
T12
T13
Interrupt Bus
XE167FM, XE167GM, XE167HM, XE167KM
..
..
MAC Unit
Interrupt & PEC
CCU60
CPU
T12
T13
49
XE166 Family Derivatives / Base Line
DSRAM
RS232,
USICx
IIC, IIS
2 Ch.,
Buffer
64 x
LIN,
SPI,
..
..
Functional Description
RS232,
USIC0
IIC , IIS
2 Ch.,
Buffer
64 x
LIN,
SPI,
MCHK
Debug Support
WDT
LXBus Control
RTC
MC_XY_BLOCKDIAGRAM
External Bus
Control
OCDS
EBC
Multi
CAN
V2.0, 2009-03
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