UPD70F3744GJ-GAE-AX Renesas Electronics America, UPD70F3744GJ-GAE-AX Datasheet - Page 226

• Manufacturer Part Number: UPD70F3744GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3744GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 128
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JJ3
R01UH0016EJ0400 Rev.4.00
Sep 30, 2010
(n = 0 to 8)
TPnCTL1
After reset: 00H
Cautions 1. The TPnEST bit is valid only in the external trigger pulse output
TPnEEE
The TPnEEE bit selects whether counting is performed with the internal count clock
or the valid edge of the external event count input.
TPnEST
TPnMD2
0
1
0
1
7
0
0
0
0
0
1
1
1
1
Generate a valid signal for external trigger input.
• In one-shot pulse output mode: A one-shot pulse is output with writing
• In external trigger pulse output mode: A PWM waveform is output with
Disable operation with external event count input.
(Perform counting with the count clock selected by the TPnCTL0.TPnCK0
to TPnCK2 bits.)
Enable operation with external event count input.
(Perform counting at the valid edge of the external event count input
signal.)
2. External event count input is selected in the external event count
3. Set the TPnEEE and TPnMD2 to TPnMD0 bits when the
TPnEST TPnEEE
TPnMD1
4. Be sure to clear bits 3, 4, and 7 to “0”.
R/W
<6>
mode or one-shot pulse output mode. In any other mode, writing 1
to this bit is ignored.
mode regardless of the value of the TPnEEE bit.
TPnCTL0.TPnCE bit = 0. (The same value can be written when the
TPnCE bit = 1.) The operation is not guaranteed when rewriting is
performed with the TPnCE bit = 1.
performed, clear the TPnCE bit to 0 and then set the bits again.
0
0
1
1
0
0
1
1
Address: TP0CTL1 FFFFF591H, TP1CTL1 FFFFF5A1H,
TPnMD0
<5>
0
1
0
1
0
1
0
1
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
TP2CTL1 FFFFF5B1H, TP3CTL1 FFFFF5C1H,
TP4CTL1 FFFFF5D1H, TP5CTL1 FFFFF5E1H,
TP6CTL1 FFFFF5F1H, TP7CTL1 FFFFF601H,
TP8CTL1 FFFFF611H
Interval timer mode
External event count mode
External trigger pulse output mode
One-shot pulse output mode
PWM output mode
Free-running timer mode
Pulse width measurement mode
Setting prohibited
4
0
Software trigger control
Count clock selection
1 to the TPnEST bit as the trigger.
3
0
−
Timer mode selection
writing 1 to the TPnEST bit as the
trigger.
TPnMD2 TPnMD1 TPnMD0
2
If rewriting was mistakenly
1
0
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