UPD70F3744GJ-GAE-AX Renesas Electronics America, UPD70F3744GJ-GAE-AX Datasheet - Page 671

• Manufacturer Part Number: UPD70F3744GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3744GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 128
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JJ3
R01UH0016EJ0400 Rev.4.00
Sep 30, 2010
Maskable Interrupt
Type
Remarks 1. Default Priority: The priority order when two or more maskable interrupt requests occur at the same time.
Classification Default
2. The execution address of the illegal instruction when an illegal opcode exception occurs is calculated by
Restored PC:
nextPC:
(Restored PC − 4).
Priority
55
56
57
58
59
60
61
62
63
64
65
66
67
68
INTP8
INTTP6OV
INTTP6CC0
INTTP6CC1
INTTP7OV
INTTP7CC0
INTTP7CC1
INTTP8OV
INTTP8CC0
INTTP8CC1
INTCB5R
INTCB5T
INTUA3R
INTUA3T
Name
The highest priority is 0.
The priority order of non-maskable interrupt is INTWDT2 > NMI.
The value of the program counter (PC) saved to EIPC, FEPC, or DBPC when interrupt
servicing is started. Note, however, that the restored PC when a non-maskable or
maskable interrupt is acknowledged while one of the following instructions is being
executed does not become the nextPC (if an interrupt is acknowledged during interrupt
execution, execution stops, and then resumes after the interrupt servicing has finished).
• Load instructions (SLD.B, SLD.BU, SLD.H, SLD.HU, SLD.W)
• Division instructions (DIV, DIVH, DIVU, DIVHU)
• PREPARE, DISPOSE instructions (only if an interrupt is generated before the stack
The PC value that starts the processing following interrupt/exception processing.
pointer is updated)
External interrupt pin input edge
detection (INTP8)
TMP6 overflow
TMP6 capture 0/compare 0 match
TMP6 capture 1/compare 1 match
TMP7 overflow
TMP7 capture 1/compare 0 match
TMP7 capture 1/compare 1 match
TMP8 overflow
TMP8 capture 0/compare 0 match
TMP8 capture 1/compare 1 match
CSIB5 reception completion
CSIB5 consecutive transmission
write enable
UART3 consecutive reception
completion
UARTA3 consecutive transmission
enable
Table 19-1. Interrupt Source List (3/3)
CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION
Trigger
Generating
Pin
TMP6
TMP6
TMP6
TMP7
TMP7
TMP7
TMP8
TMP8
TMP8
CSIB5
CSIB5
UARTA3
UARTA3
Unit
0470H
0480H
0490H
04A0H
04B0H
04C0H
04D0H
04E0H
04F0H
0500H
0510H
0520H
0530H
0540H
Exception
Code
00000470H
00000480H
00000490H
000004A0H
000004B0H
000004C0H
000004D0H
000004E0H
000004F0H
00000500H
00000510H
00000520H
00000530H
00000540H
Address
Handler
nextPC
nextPC
nextPC
nextPC
nextPC
nextPC
nextPC
nextPC
nextPC
nextPC
nextPC
nextPC
nextPC
nextPC
Restored
PC
Page 655 of 892
PIC8
TP6OVIC
TP6CCIC0
TP6CCIC1
TP7OVIC
TP7CCIC0
TP7CCIC1
TP8OVIC
TP8CCIC0
TP8CCIC1
CB5RIC
CB5TIC
UA3RIC
UA3TIC
Interrupt
Register
Control