UPD70F3744GJ-GAE-AX Renesas Electronics America, UPD70F3744GJ-GAE-AX Datasheet - Page 434

• Manufacturer Part Number: UPD70F3744GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3744GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 128
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JJ3
R01UH0016EJ0400 Rev.4.00
Sep 30, 2010
(1) Real-time output buffer registers nL, nH (RTBLn, RTBHn)
Note After setting the real-time output port, set output data to the RTBLn and RTBHn registers by the time a real-time
4 bits × 1 channel,
2 bits × 1 channel
6 bits × 1 channel
The RTBLn and RTBHn registers are 4-bit registers that hold preset output data.
These registers are mapped to independent addresses in the peripheral I/O register area.
These registers can be read or written in 8-bit or 1-bit units.
Reset sets these registers to 00H.
If an operation mode of 4 bits × 1 channel or 2 bits × 1 channel is specified (RTPCn.BYTEn bit = 0), data can be
individually set to the RTBLn and RTBHn registers. The data of both these registers can be read at once by
specifying the address of either of these registers.
If an operation mode of 6 bits × 1 channel is specified (BYTEn bit = 1), 8-bit data can be set to both the RTBLn and
RTBHn registers by writing the data to either of these registers. Moreover, the data of both these registers can be
read at once by specifying the address of either of these registers.
Table 12-2 shows the operation when the RTBLn and RTBHn registers are manipulated.
output trigger is generated.
Operation Mode
RTBLn
RTBHn
Cautions 1. When writing to bits 6 and 7 of the RTBHn register, always write 0.
Remark n = 0, 1
After reset: 00H
Table 12-2. Operation During Manipulation of RTBLn and RTBHn Registers
2. Accessing the RTBLn and RTBHn registers is prohibited in the following
0
•
•
RTBLn
RTBHn
RTBLn
RTBHn
statuses. For details, see 3.4.8 (2) Accessing specific on-chip peripheral I/O
registers.
Register to Be
Manipulated
When the CPU operates with the subclock and the main clock oscillation is
stopped
When the CPU operates with the internal oscillation clock
R/W
0
Address: RTBL0 FFFFF6E0H, RTBH0 FFFFF6E2H,
RTBHn5 RTBHn4
RTBHn
RTBHn
RTBHn
RTBHn
Higher 4 Bits
RTBL1 FFFFF6F0H, RTBH1 FFFFF6F2H
CHAPTER 12 REAL-TIME OUTPUT FUNCTION (RTO)
Read
RTBLn3 RTBLn2
RTBLn
RTBLn
RTBLn
RTBLn
Lower 4 Bits
Invalid
RTBHn
RTBHn
RTBHn
RTBLn1
Higher 4 Bits
RTBLn0
Write
RTBLn
Invalid
RTBLn
RTBLn
Note
Lower 4 Bits
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