SAK-XC2287M-104F80L AA Infineon Technologies, SAK-XC2287M-104F80L AA Datasheet - Page 63

• Manufacturer Part Number: SAK-XC2287M-104F80L AA
• Description: IC MCU 32BIT FLASH 144-LQFP
• Manufacturer: Infineon Technologies
• Series: XC22xxMr

Specifications of SAK-XC2287M-104F80L AA

• Core Processor: C166SV2
• Core Size: 16/32-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, I²C, LIN, SPI, SSC, UART/USART, USI
• Peripherals: I²S, POR, PWM, WDT
• Number Of I /o: 118
• Program Memory Size: 832KB (832K x 8)
• Program Memory Type: FLASH
• Ram Size: 50K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: SP000436560

The XC228xM includes an excellent mechanism to identify and process exceptions or
error conditions that arise during run-time, the so-called ‘Hardware Traps’. A hardware
trap causes an immediate non-maskable system reaction similar to a standard interrupt
service (branching to a dedicated vector table location). The occurrence of a hardware
trap is also indicated by a single bit in the trap flag register (TFR). Unless another higher-
priority trap service is in progress, a hardware trap will interrupt any ongoing program
execution. In turn, hardware trap services can normally not be interrupted by standard
or PEC interrupts.
Table 8
Table 8
Exception Condition
Reset Functions
Class A Hardware Traps:
•
•
•
•
Class B Hardware Traps:
•
•
•
•
•
•
Reserved
Software Traps:
•
1) Register VECSEG defines the segment where the vector table is located to.
Data Sheet
Bitfield VECSC in register CPUCON1 defines the distance between two adjacent vectors. This table
represents the default setting, with a distance of 4 (two words) between two vectors.
System Request 0
Stack Overflow
Stack Underflow
Software Break
System Request 1
Memory Protection
Undefined Opcode
Memory Access Error
Protected Instruction
Fault
Illegal Word Operand
Access
TRAP Instruction
shows all possible exceptions or error conditions that can arise during runtime:
Trap Summary
Trap
Flag
–
SR0
STKOF
STKUF
SOFTBRK
SR1
MPR/W/X
UNDOPC
ACER
PRTFLT
ILLOPA
–
–
XC2000 Family Derivatives / Base Line
Trap
Vector
RESET
SR0TRAP
STOTRAP
STUTRAP
SBRKTRAP
BTRAP
BTRAP
BTRAP
BTRAP
BTRAP
BTRAP
–
–
63
XC2287M, XC2286M, XC2285M
Vector
Location
xx’0000
xx’0008
xx’0010
xx’0018
xx’0020
xx’0028
xx’0028
xx’0028
xx’0028
xx’0028
xx’0028
[2C
Any
[xx’0000
xx’01FC
in steps of
4
H
H
- 3C
Functional Description
H
H
H
H
H
H
H
H
H
H
H
H
H
1)
]
H
-
] [0B
Trap
Number
00
02
04
06
08
0A
0A
0A
0A
0A
0A
0F
Any
[00
7F
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
]
]
-
-
V2.0, 2009-03
Trap
Priority
III
II
II
II
II
I
I
I
I
I
I
–
Current
CPU
Priority