PIC18F2539T-I/SO Microchip Technology, PIC18F2539T-I/SO Datasheet
PIC18F2539T-I/SO
Specifications of PIC18F2539T-I/SO
Related parts for PIC18F2539T-I/SO
PIC18F2539T-I/SO Summary of contents
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... PGM RB6 SCLK RB7 SDATA Legend Input Output Power Note 1: See Section 5.3 for more detail. 2010 Microchip Technology Inc. PIC18FXX39 2.1 Hardware Requirements In High Voltage ICSP mode, the PIC18FXX39 requires programming two programmable power supplies: one for V one for MCLR/V minimum resolution of 0 ...
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... RB3 5 36 RB2 6 35 RB1 7 34 RB0 RD7 11 30 RD6 12 29 RD5 28 13 RD4 14 27 RC7 15 26 RC6 16 25 RC5 17 24 RC4 18 23 RD3 19 22 RD2 20 21 OSC2 33 OSC1 PIC18FXX39 RE2 RE1 26 RE0 25 RA5 24 23 RA4 2010 Microchip Technology Inc. ...
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... ID Location 8 300000h CONFIG1L 300001h CONFIG1H 300002h CONFIG2L 300003h CONFIG2H 3FFFFEh Device ID1 3FFFFFh Device ID2 2010 Microchip Technology Inc. PIC18FXX39 TABLE 2-2: IMPLEMENTATION OF CODE MEMORY Device PIC18F2439 0000h - 2FFFh (12 Kbytes) PIC18F2539 0000h - 5FFFh (24 Kbytes) PIC18F4439 0000h - 2FFFh (12 Kbytes) PIC18F4539 0000h - 5FFFh (24 Kbytes) 2 ...
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... Start Blank Check No Perform Bulk Is part blank Erase ? Yes Program Memory Program IDs Program Data Verify Program Verify IDs Verify Data Program Configuration Bits Verify Configuration Bits Done Preliminary 2010 Microchip Technology Inc. ...
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... PP IH pin is dedicated to the programming function and ceases general purpose I/O pin. The sequence that enters the device into the Programming/Verify mode places all unused I/O’s in the high impedance state. 2010 Microchip Technology Inc. FIGURE 2-5: MCLR/V PP accessed and V ...
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... DS30480C-page 6 2.6.2 CORE INSTRUCTION The core instruction passes a 16-bit instruction to the CPU core for execution. This is needed to setup registers as appropriate for use with other commands 16-bit Data Payload SDATA = Input Preliminary P5A Fetch Next 4-bit Command 2010 Microchip Technology Inc. ...
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... Yes device Continue blank? No Abort 2010 Microchip Technology Inc. 3.2 High Voltage ICSP Bulk Erase Erasing code or data EEPROM is accomplished by writing an “erase option” to address 3C0004h. Code memory may be erased portions at a time, or the user may erase the entire device in one action. “Bulk Erase” ...
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... BCF EECON1, CFGS MOVLW 20h MOVWF TBLPTRU MOVLW 00h MOVWF TBLPTRH MOVLW 00h MOVWF TBLPTRL BSF EECON1, WREN BSF EECON1, FREE MOVLW 55h MOVWF EECON2 MOVLW AAh MOVWF EECON2 BSF EECON1, WR NOP BCF EECON1, WREN Preliminary 2010 Microchip Technology Inc. ...
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... Erase Panel 1 Delay P11 + P10 Time Load 00h (Single Panel) to 3C0006h Set Code Memory Access to EE Control Registers 2010 Microchip Technology Inc. PIC18FXX39 Load 2000h to Table Pointer (Panel 2 Starting Address) Enable Memory Write and Data EEPROM Unlock Sequence and Erase the ...
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... Hold SDATA low until erase complete (P11+P10) Write 89h to 3C0004h to erase the panel 2 NOP Hold SDATA low until erase complete (P11+P10) Write 8Ah to 3C0004h to erase the panel 3 NOP Hold SDATA low until erase complete (P11+P10) Preliminary 2010 Microchip Technology Inc. ...
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... Write 83h to Erase Boot Block Delay P11 + P10 Time FIGURE 3-4: BULK ERASE TIMING SCLK P5 SDATA 4-bit Command 16-bit Data Payload 2010 Microchip Technology Inc. Write 88h to Erase Panel 1 Delay P11 + P10 Time Write 89h to Erase Panel P5A P5A 4-bit Command ...
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... Figure 3-7 depicts the logic necessary to completely write a PIC18FXX39 device. Note: The TBLPTR register must contain the same offset value when initiating the pro- gramming sequence as it did when the write buffers were loaded. Preliminary 2010 Microchip Technology Inc. Erase Region (64 bytes) Offset = TBLPTR<12:6> ...
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... SCLK P5 SDATA 4-bit Command 2010 Microchip Technology Inc. Core Instruction MOVLW 3Ch MOVWF TBLPTRU MOVLW 00h MOVWF TBLPTRH MOVLW 06h MOVWF TBLPTRL Write 00h to 3C0006h to enable single panel writes. BSF EECON1, EEPGD BCF EECON1, CFGS MOVLW <Addr[21:16]> MOVWF TBLPTRU MOVLW < ...
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... Start Configure Device for Single Panel Write Load 8 Bytes to Write Buffer at <Addr> Start Write Sequence and Hold SCLK High Until Done Delay P9 and Pull SCLK Low Delay P10 Increment Address locations done? Preliminary 2010 Microchip Technology Inc. All Yes End ...
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... To continue writing data, repeat step 8, where the Address Pointer is incremented each iteration of the loop. 2010 Microchip Technology Inc. Core Instruction MOVLW 3Ch MOVWF TBLPTRU MOVLW 00h MOVWF TBLPTRH MOVLW 06h MOVWF TBLPTRL Write 00h to 3C0006h to enable single panel writes ...
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... PROGRAM DATA FLOW Start Set Address Set Data Enable Write Unlock Sequence 55h - EECON2 AAh - EECON2 Start Write Sequence Delay P11+P10 for Write to Occur No Done? Yes Done P10 P11 Data EEPROM 16-bit Write Time Data Payload 2010 Microchip Technology Inc. ...
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... Step 7: Wait for P11 and then disable writes. 0000 94 A6 Repeat steps 2 through 7 to write more data. 2010 Microchip Technology Inc. Core Instruction BCF EECON1, EEPGD BCF EECON1, CFGS MOVLW <Addr> MOVWF EEADR MOVLW <Data> MOVWF EEDATA ...
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... MOVWF TBLPTRH MOVLW 00h MOVWF TBLPTRL Write 2 bytes and post-increment address by 2 Write 2 bytes and post-increment address by 2 Write 2 bytes and post-increment address by 2 Write 2 bytes and start programming NOP - hold SCLK high for time P9 Preliminary 2010 Microchip Technology Inc. ...
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... Address Program LSB Delay P9 Time for Write Done 2010 Microchip Technology Inc. 3.7 Configuration Bits Programming Unlike code memory, the configuration bits are programmed a byte at a time. The “Table Write, Begin Programming” 4-bit command (1111) is used, but only 8 bits of the following 16-bit payload will be written. The LSB of the payload will be written to even addresses, and the MSB will be written to odd addresses ...
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... Shift Out Data P14 LSb Shift Data Out SDATA = Output Preliminary READ DATA EEPROM FLOW Start Set Address Read Byte Move to TABLAT Shift Out Data No Done? Yes Done P5A MSb Fetch Next 4-bit Command SDATA = Input 2010 Microchip Technology Inc. ...
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... SDATA = Input 2010 Microchip Technology Inc. delay of P6 must be introduced after the falling edge of the 8th SCLK of the operand to allow SDATA to transition from an input to an output. During this time, SCLK must be held low (see Table 4-2). This operation also increments the Table Pointer by one, pointing to the next byte in code memory for the next read ...
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... The result may then be immediately compared to the appropriate data in the programmer’s memory for verification. Refer to Section 4.1 for implementation details of reading data EEPROM. Preliminary Does No Failure, data? Report Error Yes All ID locations verified? Yes Done 2010 Microchip Technology Inc. ...
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... TABLE 5-1: DEVICE ID VALUE Device PIC18F2439 PIC18F2539 PIC18F4439 PIC18F4539 2010 Microchip Technology Inc. 5.3 Low Voltage Programming (LVP) Bit The LVP bit in configuration register, CONFIG4L, enables low voltage ICSP programming. The LVP bit to setting defaults to a ‘1’ from the factory. ...
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... CP1 CP0 0000 1111 — — 1100 0000 WRT1 WRT0 0000 1111 — — 1110 0000 EBTR1 EBTR0 0000 1111 — — 0100 0000 REV1 REV0 Table 5-1 DEV4 DEV3 Table 5-1 2010 Microchip Technology Inc. ...
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... STVREN CONFIG4L CP0 CONFIG5L CP1 CONFIG5L CP2 CONFIG5L 2010 Microchip Technology Inc. Description Oscillator Selection bits 111 = Reserved 110 = HS oscillator w/ PLL enabled 101 = EC oscillator w/ OSC2 configured as RA6 100 = EC oscillator w/ OSC2 configured as “divide by 4 clock output” 011 = Reserved 010 = HS oscillator ...
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... Device ID bits are used with the DEV2:DEV0 bits in the DEVID1 register to identify part number. Device ID bits are used with the DEV10:DEV3 bits in the DEVID2 register to identify part number. These bits are used to indicate the revision of the device. Preliminary 2010 Microchip Technology Inc. ...
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... An option to not include the configuration word information may be provided. When embedding configuration word information in the HEX file, it should start at address 300000h. Microchip Technology Inc. feels strongly that this feature is important for the benefit of the end customer. 2010 Microchip Technology Inc. 5.5 ...
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... Checksum Calculation Method Preliminary Blank Seed Seed at 0 Checksum at 0 and Max A2BF A26A A215 A4A5 A49B A43C E2A2 E298 E239 029E 0294 028A A2BF A26A A215 A4A5 A49B A43C E2A2 E298 E239 029E 0294 028A 2010 Microchip Technology Inc. ...
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... CFGW = Configuration Word SUM[a:b] = Sum of locations inclusive SUM_ID = Byte-wise sum of lower four bits of all customer ID locations + = Addition & = Bit-wise AND 2010 Microchip Technology Inc. Checksum Calculation Method Preliminary PIC18FXX39 Blank Seed Seed at 0 Checksum at 0 and Max A2BF A26A A215 ...
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... EEPROM information must be included. An option to not include the data EEPROM information may be provided. When embedding data EEPROM information in the HEX file, it should start at address F00000h. Microchip Technology Inc. believes that this feature is important for the benefit of the end customer. DS30480C-page 30 PIC18FXX39 Preliminary ...
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... Input Data Hold Time from MCLR/V Setup Time to MCLR/V P13 Tset2 V DD Data Out Valid from SCLK P14 Tvalid PGM Setup Time to MCLR/V P15 Tset3 2010 Microchip Technology Inc. PIC18FXX39 Min Max 9.00 13.25 2.00 5.50 2.00 5.50 4.50 5.50 — ...
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... PIC18FXX39 NOTES: DS30480C-page 32 Preliminary 2010 Microchip Technology Inc. ...
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... REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 Preliminary 2010 Microchip Technology Inc. EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 ...