ATMEGA169-16MI Atmel, ATMEGA169-16MI Datasheet - Page 183

• Manufacturer Part Number: ATMEGA169-16MI
• Description: IC AVR MCU 16K 16MHZ IND 64-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA169-16MI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• For Use With: ATAVRBFLY - KIT EVALUATION AVR BUTTERFLYATSTK502 - MOD EXPANSION AVR STARTER 500
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Two-wire Mode
2514P–AVR–07/06
Note that the first two instructions is for initialization only and needs only to be executed
once.These instructions sets Three-wire mode and positive edge Shift Register clock.
The loop is repeated until the USI Counter Overflow Flag is set.
The USI Two-wire mode is compliant to the Inter IC (TWI) bus protocol, but without slew
rate limiting on outputs and input noise filtering. Pin names used by this mode are SCL
and SDA.
Figure 79. Two-wire Mode Operation, Simplified Diagram
Figure 79 shows two USI units operating in Two-wire mode, one as Master and one as
Slave. It is only the physical layer that is shown since the system operation is highly
dependent of the communication scheme used. The main differences between the Mas-
ter and Slave operation at this level, is the serial clock generation which is always done
by the Master, and only the Slave uses the clock control unit. Clock generation must be
implemented in software, but the shift operation is done automatically by both devices.
Note that only clocking on negative edge for shifting data is of practical use in this mode.
The slave can insert wait states at start or end of transfer by forcing the SCL clock low.
This means that the Master must always check if the SCL line was actually released
after it has generated a positive edge.
Since the clock also increments the counter, a counter overflow can be used to indicate
that the transfer is completed. The clock is generated by the master by toggling the
USCK pin via the PORT Register.
The data direction is not given by the physical layer. A protocol, like the one used by the
TWI-bus, must be implemented to control the data flow.
SLAVE
MASTER
Bit7
Bit7
Bit6
Bit6
Bit5
Bit5
Bit4
Bit4
Bit3
Bit3
Bit2
Bit2
Bit1
Bit1
Bit0
Bit0
Two-wire Clock
Control Unit
PORTxn
ATmega169/V
HOLD
SCL
SDA
SCL
SDA
SCL
VCC
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