ATMEGA169-16MI Atmel, ATMEGA169-16MI Datasheet - Page 188

• Manufacturer Part Number: ATMEGA169-16MI
• Description: IC AVR MCU 16K 16MHZ IND 64-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA169-16MI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• For Use With: ATAVRBFLY - KIT EVALUATION AVR BUTTERFLYATSTK502 - MOD EXPANSION AVR STARTER 500
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

188
ATmega169/V
Table 83. Relations between USIWM1..0 and the USI Operation
Note:
USIWM1
0
0
1
1
1. The DI and USCK pins are renamed to Serial Data (SDA) and Serial Clock (SCL)
respectively to avoid confusion between the modes of operation.
USIWM0
0
1
0
1
Description
Outputs, clock hold, and start detector disabled. Port pins operates as
normal.
Three-wire mode. Uses DO, DI, and USCK pins.
The Data Output (DO) pin overrides the corresponding bit in the PORT
Register in this mode. However, the corresponding DDR bit still
controls the data direction. When the port pin is set as input the pins
pull-up is controlled by the PORT bit.
The Data Input (DI) and Serial Clock (USCK) pins do not affect the
normal port operation. When operating as master, clock pulses are
software generated by toggling the PORT Register, while the data
direction is set to output. The USITC bit in the USICR Register can be
used for this purpose.
Two-wire mode. Uses SDA (DI) and SCL (USCK) pins
The Serial Data (SDA) and the Serial Clock (SCL) pins are bi-
directional and uses open-collector output drives. The output drivers
are enabled by setting the corresponding bit for SDA and SCL in the
DDR Register.
When the output driver is enabled for the SDA pin, the output driver will
force the line SDA low if the output of the Shift Register or the
corresponding bit in the PORT Register is zero. Otherwise the SDA
line will not be driven (i.e., it is released). When the SCL pin output
driver is enabled the SCL line will be forced low if the corresponding bit
in the PORT Register is zero, or by the start detector. Otherwise the
SCL line will not be driven.
The SCL line is held low when a start detector detects a start condition
and the output is enabled. Clearing the Start Condition Flag (USISIF)
releases the line. The SDA and SCL pin inputs is not affected by
enabling this mode. Pull-ups on the SDA and SCL port pin are
disabled in Two-wire mode.
Two-wire mode. Uses SDA and SCL pins.
Same operation as for the Two-wire mode described above, except
that the SCL line is also held low when a counter overflow occurs, and
is held low until the Counter Overflow Flag (USIOIF) is cleared.
(1)
.
2514P–AVR–07/06