ATMEGA169-16MI Atmel, ATMEGA169-16MI Datasheet - Page 36

• Manufacturer Part Number: ATMEGA169-16MI
• Description: IC AVR MCU 16K 16MHZ IND 64-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA169-16MI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• For Use With: ATAVRBFLY - KIT EVALUATION AVR BUTTERFLYATSTK502 - MOD EXPANSION AVR STARTER 500
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Brown-out Detector
Internal Voltage Reference
Watchdog Timer
Port Pins
JTAG Interface and
On-chip Debug System
36
ATmega169/V
If the Brown-out Detector is not needed by the application, this module should be turned
off. If the Brown-out Detector is enabled by the BODLEVEL Fuses, it will be enabled in
all sleep modes, and hence, always consume power. In the deeper sleep modes, this
will contribute significantly to the total current consumption. Refer to “Brown-out Detec-
tion” on page 40 for details on how to configure the Brown-out Detector.
The Internal Voltage Reference will be enabled when needed by the Brown-out Detec-
tion, the Analog Comparator or the ADC. If these modules are disabled as described in
the sections above, the internal voltage reference will be disabled and it will not be con-
suming power. When turned on again, the user must allow the reference to start up
before the output is used. If the reference is kept on in sleep mode, the output can be
used immediately. Refer to “Internal Voltage Reference” on page 42 for details on the
start-up time.
If the Watchdog Timer is not needed in the application, the module should be turned off.
If the Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence,
always consume power. In the deeper sleep modes, this will contribute significantly to
the total current consumption. Refer to “Watchdog Timer” on page 43 for details on how
to configure the Watchdog Timer.
When entering a sleep mode, all port pins should be configured to use minimum power.
The most important is then to ensure that no pins drive resistive loads. In sleep modes
where both the I/O clock (clk
ers of the device will be disabled. This ensures that no power is consumed by the input
logic when not needed. In some cases, the input logic is needed for detecting wake-up
conditions, and it will then be enabled. Refer to the section “Digital Input Enable and
Sleep Modes” on page 59 for details on which pins are enabled. If the input buffer is
enabled and the input signal is left floating or have an analog signal level close to V
the input buffer will use excessive power.
For analog input pins, the digital input buffer should be disabled at all times. An analog
signal level close to V
mode. Digital input buffers can be disabled by writing to the Digital Input Disable Regis-
ters (DIDR1 and DIDR0). Refer to “Digital Input Disable Register 1 – DIDR1” on page
192 and “Digital Input Disable Register 0 – DIDR0” on page 209 for details.
If the On-chip debug system is enabled by the OCDEN Fuse and the chip enter Power
down or Power save sleep mode, the main clock source remains enabled. In these
sleep modes, this will contribute significantly to the total current consumption. There are
three alternative ways to avoid this:
•
•
•
The TDO pin is left floating when the JTAG interface is enabled while the JTAG TAP
controller is not shifting data. If the hardware connected to the TDO pin does not pull up
the logic level, power consumption will increase. Note that the TDI pin for the next
device in the scan chain contains a pull-up that avoids this problem. Writing the JTD bit
in the MCUCSR register to one or leaving the JTAG fuse unprogrammed disables the
JTAG interface.
Disable OCDEN Fuse.
Disable JTAGEN Fuse.
Write one to the JTD bit in MCUCSR.
CC
/2 on an input pin can cause significant current even in active
I/O
) and the ADC clock (clk
ADC
) are stopped, the input buff-
2514P–AVR–07/06
CC
/2,