PIC16LF819T-E/SO Microchip Technology, PIC16LF819T-E/SO Datasheet - Page 137

• Manufacturer Part Number: PIC16LF819T-E/SO
• Description: IC PIC MCU FLASH 2KX14 18SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16LF819T-E/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 18-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification

14.2.4
Each of the 16 possible bidirectional endpoints has its
own independent control register, UEPn (where ‘n’ rep-
resents the endpoint number). Each register has an
identical complement of control bits. The prototype is
shown in Register 14-4.
The EPHSHK bit (UEPn<4>) controls handshaking for
the endpoint; setting this bit enables USB handshaking.
Typically, this bit is always set except when using
isochronous endpoints.
The EPCONDIS bit (UEPn<3>) is used to enable or
disable USB control operations (SETUP) through the
endpoint.
transactions. Note that the corresponding EPINEN and
EPOUTEN bits must be set to enable IN and OUT
REGISTER 14-4:
© 2008 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-5
bit 4
bit 3
bit 2
bit 1
bit 0
U-0
—
USB ENDPOINT CONTROL
Clearing
Unimplemented: Read as ‘0’
EPHSHK: Endpoint Handshake Enable bit
1 = Endpoint handshake enabled
0 = Endpoint handshake disabled (typically used for isochronous endpoints)
EPCONDIS: Bidirectional Endpoint Control bit
If EPOUTEN = 1 and EPINEN = 1:
1 = Disable Endpoint n from control transfers; only IN and OUT transfers allowed
0 = Enable Endpoint n for control (SETUP) transfers; IN and OUT transfers also allowed
EPOUTEN: Endpoint Output Enable bit
1 = Endpoint n output enabled
0 = Endpoint n output disabled
EPINEN: Endpoint Input Enable bit
1 = Endpoint n input enabled
0 = Endpoint n input disabled
EPSTALL: Endpoint Stall Indicator bit
1 = Endpoint n has issued one or more STALL packets
0 = Endpoint n has not issued any STALL packets
U-0
—
UEPn: USB ENDPOINT n CONTROL REGISTER (UEP0 THROUGH UEP15)
this
bit
W = Writable bit
‘1’ = Bit is set
enables
U-0
—
SETUP
EPHSHK
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
EPCONDIS
R/W-0
transactions. For Endpoint 0, this bit should always be
cleared
Endpoint 0 as the default control endpoint.
The EPOUTEN bit (UEPn<2>) is used to enable or dis-
able USB OUT transactions from the host. Setting this
bit enables OUT transactions. Similarly, the EPINEN bit
(UEPn<1>) enables or disables USB IN transactions
from the host.
The EPSTALL bit (UEPn<0>) is used to indicate a
STALL condition for the endpoint. If a STALL is issued
on a particular endpoint, the EPSTALL bit for that end-
point pair will be set by the SIE. This bit remains set
until it is cleared through firmware, or until the SIE is
reset.
PIC18F2450/4450
since
EPOUTEN
R/W-0
the
USB
x = Bit is unknown
EPINEN
R/W-0
specifications
DS39760D-page 135
EPSTALL
R/W-0
identify
bit 0
(1)