DSPIC30F5016-20I/PT Microchip Technology, DSPIC30F5016-20I/PT Datasheet - Page 12
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DSPIC30F5016-20I/PT
Manufacturer Part Number
DSPIC30F5016-20I/PT
Description
IC DSPIC MCU/DSP 66K 80TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F5011T-20IPT.pdf
(34 pages)
3.DSPIC30F6010T-20IPF.pdf
(6 pages)
4.DSPIC30F5016-20IPT.pdf
(100 pages)
Specifications of DSPIC30F5016-20I/PT
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
68
Program Memory Size
66KB (22K x 24)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TFQFP
For Use With
AC164320 - MODULE SKT MPLAB PM3 80TQFPAC30F007 - MODULE SKT FOR DSPIC30F 80TQFP
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Other names
DSPIC30F501620IPT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F5016-20I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
dsPIC30F Family Reference Manual
16. Page 6-6, Section 6.2 Non-Maskable
17. Page 6-7, Section 6.2.2 Hard Traps
18. Page 6-8, Section 6.2.2.3 Address Error
19. Page 6-10, Section 6.2.5 Wake-up from
20. Page 6-43, Table 6-3: Special Function
DS80169E-page 12
On page 6-6, Section 6.2 Non-Maskable Traps,
the second paragraph should be replaced with the
following:
On page 6-7, Section 6.2.2 Hard Traps, paragraph
1 should be replaced with the following:
On page 6-8, Section 6.2.2.3 Address Error Trap
(Hard Trap, Level 13), the following additional cir-
cumstances under which an Address Error Trap
may occur, should be included in the numbered list
of items:
On page 6-10, Section 6.2.5 Wake-up from SLEEP
and IDLE, the existing note should be replaced
with the following:
On page 6-43, Table 6-3: Special Function
Registers Associated with Interrupt Controller, row
3, Bit 0, SFR Name: IFS0, should be replaced with
the following:
INT0IF
Traps
Trap (Hard Trap, Level 13)
SLEEP and IDLE
Registers Associated with Interrupt
Controller
The dsPIC30F has four implemented sources of non-maskable traps:
Hard traps include exceptions of priority level 13 through level 15, inclusive. The address error
(level 13) and oscillator error (level 14) traps fall into this category.
4.Execution of a “BRA
5.Executing instructions after modifying the PC to point to unimplemented program memory
•Oscillator Failure Trap
•Stack Error Trap
•Address Error Trap
•Arithmetic Error Trap
literal is an unimplemented program memory address.
addresses. The PC may be modified by loading a value into the stack and executing a RETURN
instruction.
Note:
User interrupt sources that are assigned to CPU priority level 0 cannot wake the CPU
from SLEEP or IDLE mode, because the interrupt source is effectively disabled. To
use an interrupt as a wake-up source, the CPU priority level for the interrupt must be
assigned to CPU priority level 1 or greater.
#literal” instruction or a “GOTO
#literal” instruction, where
2004 Microchip Technology Inc.