DSPIC30F5016-20I/PT Microchip Technology, DSPIC30F5016-20I/PT Datasheet - Page 22
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DSPIC30F5016-20I/PT
Manufacturer Part Number
DSPIC30F5016-20I/PT
Description
IC DSPIC MCU/DSP 66K 80TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F5011T-20IPT.pdf
(34 pages)
3.DSPIC30F6010T-20IPF.pdf
(6 pages)
4.DSPIC30F5016-20IPT.pdf
(100 pages)
Specifications of DSPIC30F5016-20I/PT
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
68
Program Memory Size
66KB (22K x 24)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TFQFP
For Use With
AC164320 - MODULE SKT MPLAB PM3 80TQFPAC30F007 - MODULE SKT FOR DSPIC30F 80TQFP
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Other names
DSPIC30F501620IPT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F5016-20I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
dsPIC30F Family Reference Manual
41. Page 22-12, Equation 22-1 DCI Bit Clock
42. Page 22-24, Section 22.5.5.3 I
43. Page 23-38, Section 23.5.2 Disable Mode
44. Pages 23-22 through 23-27, Table 23-1
DS80169E-page 22
On page 22-12, Equation 22-1: DCI Bit Clock
Generator Value, should be replaced by the
following:
On page 22-24, Section 22.5.5.3 I
Justification, paragraph 2 should be replaced by
the following:
On page 23-38, Section 23.5.2 Disable Mode, add
the following note to the end.
On pages 23-22 through 23-27 in Tables 23-1 and
23-2, the nomenclature of the CAN module trans-
mit and receive buffer registers as well as the
addresses of the CAN2 module registers should
be changed/corrected as follows:
Generator Value
Justification
and Table 23-2 CAN1/CAN2 Register Map
Equation 22-1: DCI Bit Clock Generator Value
If DJST = 1, the I
presented on the CSDO pin during the same serial clock cycle as the rising or falling edge of
the FS signal. After the data word has been transmitted, the state of the CSDO pin is dictated
by the CSDOM (DCICON1<6>) bit.
Note:
Typically, if the CAN module is allowed to transmit in a particular mode of operation
and a transmission is requested immediately after the CAN module has been placed
in that mode of operation, the module waits for 11 consecutive recessive bits on the
bus before starting transmission. If the user switches to Disable Mode within this
11-bit period, then this transmission is aborted and the corresponding TXABT bit is
set and TXREQ bit is cleared.
2
S Data
2
S data transfers will be MSb left justified. The MSb of the data word will be
2
S Data
BCG<11:0>
=
- - - - - - - - - - 1
2f
f
CSCK
CY
–
2004 Microchip Technology Inc.