DSPIC30F5016-20I/PT Microchip Technology, DSPIC30F5016-20I/PT Datasheet - Page 3
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DSPIC30F5016-20I/PT
Manufacturer Part Number
DSPIC30F5016-20I/PT
Description
IC DSPIC MCU/DSP 66K 80TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F5011T-20IPT.pdf
(34 pages)
3.DSPIC30F6010T-20IPF.pdf
(6 pages)
4.DSPIC30F5016-20IPT.pdf
(100 pages)
Specifications of DSPIC30F5016-20I/PT
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
68
Program Memory Size
66KB (22K x 24)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TFQFP
For Use With
AC164320 - MODULE SKT MPLAB PM3 80TQFPAC30F007 - MODULE SKT FOR DSPIC30F 80TQFP
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Other names
DSPIC30F501620IPT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F5016-20I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
5.
6.
TABLE 1:
2004 Microchip Technology Inc.
12
11
10
Bit Location
in CORCON
On page 2-37, Section 2.10.2.4 Instruction Stalls
and Program Space Visibility should be replaced
with the following:
On page 2-39, Table 2-8 dsPIC30F Core Register
Map (Continued), in the first row of the table,
correct bits names for bit 8 through bit 12 in the
CORCON register as follows:
Page 2-37, Section 2.10.2.4 Instruction
Page 2-39, Table 2-8 dsPIC30F Core
Stalls and Program Space Visibility
2.10.2.4
Register Map (Continued)
Instruction Stalls and Program Space Visibility (PSV)
CORCON BIT NAMES
(Incorrect)
Bit Name
EDT
US
When program space (PS) is mapped to data space by enabling the PSV (CORCON<2>) bit, and
the X space EA falls within the visible program space window, the read or write cycle is redirected
to the address in program space. Accessing data from program space takes up to 3 instruction
cycles.
Instructions operating in PSV address space are subject to RAW data dependencies and
consequent instruction stalls, just like any other instruction.
Consider the following code segment:
This sequence of instructions would take 5 instruction cycles to execute. 2 instruction cycles are
added to perform the PSV access via W1. Furthermore, an instruction stall cycle is inserted to
resolve the RAW data dependency caused by W2.
-
ADD W0,[W1],[W2++]; PSV = 1, W1=0x8000, PSVPAG=0xAA
MOV [W2],[W3]
(Please read as)
Bit Name
EDT
DL2
dsPIC30F Family Reference Manual
US
DS80169E-page 3