DSPIC30F5016-20I/PT Microchip Technology, DSPIC30F5016-20I/PT Datasheet - Page 2
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DSPIC30F5016-20I/PT
Manufacturer Part Number
DSPIC30F5016-20I/PT
Description
IC DSPIC MCU/DSP 66K 80TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F5011T-20IPT.pdf
(34 pages)
3.DSPIC30F6010T-20IPF.pdf
(6 pages)
4.DSPIC30F5016-20IPT.pdf
(100 pages)
Specifications of DSPIC30F5016-20I/PT
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
68
Program Memory Size
66KB (22K x 24)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TFQFP
For Use With
AC164320 - MODULE SKT MPLAB PM3 80TQFPAC30F007 - MODULE SKT FOR DSPIC30F 80TQFP
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Other names
DSPIC30F501620IPT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F5016-20I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
dsPIC30F Family Reference Manual
1.
2.
3.
4.
DS80169E-page 2
On page 2-2, Section 2.1 Introduction, paragraph
5 should be replaced with the following:
On page 2-10, Section 2.3.3 Stack Pointer Over-
flow, the last sentence in paragraph 2 should be
replaced by the following:
On page 2-34, Section 2.9.2.5 DO Loop Restric-
tions, the following paragraph and bullets should
be added to the end of this section:
On page 2-34, Section 2.9.2.5.1 Last Instruction
Restrictions, the following bullet should be added
to the end of the bulleted list:
Page 2-2, Section 2.1 Introduction
Page 2-10, Section 2.3.3 Stack Pointer
Overflow
Page 2-34, Section 2.9.2.5 DO Loop
Restrictions
Page 2-34, Section 2.9.2.5.1 Last
Instruction Restrictions
The upper 32 Kbytes of the data space memory map can optionally be mapped into program
space at any 16K program word boundary defined by the 8-bit Program Space Visibility Page
(PSVPAG) register. The program to data space mapping feature lets any instruction access
program space as if it were data space. Furthermore, RAM may be connected to the program
memory bus on devices with an external bus and used to extend the internal data RAM.
If the contents of the Stack Pointer (W15) are greater than the contents of the SPLIM register by
2 and a push operation is performed, a Stack Error Trap will not occur. The Stack Error Trap will
occur on a subsequent push operation. Thus, for example, if it is desirable to cause a Stack Error
Trap when the stack grows beyond address 0x2000 in RAM, initialize the SPLIM with the value,
0x1FFE.
The instruction that is executed two instructions before the last instruction in a DO loop should not
modify any of the following:
•CPU priority level governed by the IPL (SR<7:5>) bits
•Peripheral Interrupt Enable bits governed by the IEC0, IEC1 and IEC2 registers
•Peripheral Interrupt Priority bits governed by the IPC0 through IPC11 registers
If the restrictions above are not followed, the DO loop may execute incorrectly.
Note:
6. DISI instruction
A Stack Error Trap may be caused by any instruction that uses the contents of the
W15 register to generate an effective address (EA). Thus, if the contents of W15 are
greater than the contents of the SPLIM register by 2, and a CALL instruction is
executed, or if an interrupt occurs, a Stack Error Trap will be generated.
2004 Microchip Technology Inc.