ACE1101BEMT8 Fairchild Semiconductor, ACE1101BEMT8 Datasheet - Page 21

• Manufacturer Part Number: ACE1101BEMT8
• Description: IC MCU 1KBIT EEPROM 8TSSOP
• Manufacturer: Fairchild Semiconductor
• Series: ACEX® 11xxr

Specifications of ACE1101BEMT8

• Core Processor: ACE1001
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 6
• Program Memory Size: 1KB (1K x 8)
• Program Memory Type: EEPROM
• Eeprom Size: 64 x 8
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Connectivity: -

ACE1101 Product Family Rev. B.2
The External Event Counter mode operates similarly to the PWM
mode; however, the timer is not clocked by the instruction clock
but by transitions of the T1 input signal. The edge is selectable
through the T1C1 bit of the T1CNTRL register. A block diagram of
the timer’s External Event Counter mode of operation is shown in
Figure 16.
The T1 input should be connected to an external device that
generates a positive/negative-going pulse for each event. By
clocking the timer through T1, the number of positive/negative
transitions can be counted therefore allowing software to capture
the number of events that occur. The input signal on T1 must have
a pulse width equal to or greater than one instruction clock cycle.
The counter can be configured to sense either positive-going or
negative-going transitions on the T1 pin. The maximum frequency
at which transitions can be sensed is one-half the frequency of the
instruction clock.
As with the PWM mode, when the counter underflows the counter
is reloaded from the T1RA register and the count down
proceedsfrom the loaded value. At every underflow, a pending
flag (T1PND) located in the T1CNTRL register is set. Software
must then clear the T1PND flag and can then load the T1RA
register with an alternate value.
The counter has one interrupt (TMRI1) that is maskable through
the T1EN bit of the T1CNTRL register. However, the core is only
interrupted if the T1EN bit and the G (Global Interrupt enable) bit
of the SR is set. If interrupts are enabled, the counter will generate
an interrupt each time the T1PND flag is set (whenever timer
underflows provided that the pending flag was cleared.) The
interrupt service routine is responsible for proper handling of the
T1PND flag and the T1EN bit.
The following steps show how to properly configure Timer 1 to
operate in the External Event Counter mode. For this example, the
counter is clocked every falling edge of the T1 input signal. Follow
Underflow
Interrupt
T1
Edge Selector
Logic
16-bit Counter (TMR1)
16-bit Auto-Reload
Register (T1RA)
the instructions in parentheses to clock the counter every rising
edge.
1. Configure T1 as an input by clearing bit 2 of PORTGC.
2. Initialize T1 to input with pull-up by setting bit 2 of PORTGD.
3. Enable the global interrupt enable bit.
4. Load the initial count into the TMR1 and T1RA registers.
5. Write the appropriate control value to the T1CNTRL register
6. When the counter underflows, the interrupt service routine
- RBIT 2, PORTGC
- SBIT 2, PORTGD
- SBIT 4, STATUS
When the number of external events is detected, the counter
will reach zero; however, it will not underflow until the next
event is detected. To count N pulses, load the value N-1 into
the registers. If it is only necessary to count the number of
occurrences and no action needs to be taken at a particular
count, load the value 0xFFFF into the registers.
- LD TMR1LO, #0FFH
- LD TMR1HI, #00H
- LD T1RALO, #0FFH
- LD T1RAHI, #00H
to select External Event Counter mode, to clock every falling
edge, to set the enable bit, to clear the pending flag, and to
start the counter. (See Table 12 and Table 13)
- LD T1CNTRL, #34H (#00h) ; Setting the T1C0 bit
must clear the T1PND flag and take whatever action is
required once the number of events occurs. If the software
wishes to merely count the number of events and the
anticipated number may exceed 65,536, the interrupt service
routine should record the number of underflows by
incrementing a counter in memory. Software can then
calculate the correct event count.
- RBIT T1PND, T1CNTRL
Data
Bus
; Configure G2 as an input
; Set G2 high
; T1PND equals 3
starts the timer
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