LPC2194JBD64,151 NXP Semiconductors, LPC2194JBD64,151 Datasheet - Page 22

• Manufacturer Part Number: LPC2194JBD64,151
• Description: IC ARM7 MCU FLASH 256K 64-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC2100r

Specifications of LPC2194JBD64,151

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, Microwire, SPI, SSI, SSP, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 568-1895; 935275729151; LPC2194JBD64-S

Philips Semiconductors
9397 750 12757
Preliminary data
6.20.4 External interrupt inputs
6.20.5 Memory Mapping Control
6.20.6 Power Control
6.20.7 VPB bus
The wake-up timer ensures that the oscillator and other analog functions required for
chip operation are fully functional before the processor is allowed to execute
instructions. This is important at power on, all types of Reset, and whenever any of
the aforementioned functions are turned off for any reason. Since the oscillator and
other functions are turned off during Power-down mode, any wake-up of the
processor from Power-down mode makes use of the Wake-up Timer.
The Wake-up Timer monitors the crystal oscillator as the means of checking whether
it is safe to begin code execution. When power is applied to the chip, or some event
caused the chip to exit Power-down mode, some time is required for the oscillator to
produce a signal of sufficient amplitude to drive the clock logic. The amount of time
depends on many factors, including the rate of V
the type of crystal and its electrical characteristics (if a quartz crystal is used), as well
as any other external circuitry (e.g. capacitors), and the characteristics of the
oscillator itself under the existing ambient conditions.
The LPC2194 includes up to nine edge or level sensitive External Interrupt Inputs as
selectable pin functions. When the pins are combined, external events can be
processed as four independent interrupt signals. The External Interrupt Inputs can
optionally be used to wake up the processor from Power-down mode.
The Memory Mapping Control alters the mapping of the interrupt vectors that appear
beginning at address 0x00000000. Vectors may be mapped to the bottom of the
on-chip Flash memory, or to the on-chip static RAM. This allows code running in
different memory spaces to have control of the interrupts.
The LPC2194 supports two reduced power modes: Idle mode and Power-down
mode. In Idle mode, execution of instructions is suspended until either a Reset or
interrupt occurs. Peripheral functions continue operation during Idle mode and may
generate interrupts to cause the processor to resume execution. Idle mode eliminates
power used by the processor itself, memory systems and related controllers, and
internal buses.
In Power-down mode, the oscillator is shut down and the chip receives no internal
clocks. The processor state and registers, peripheral registers, and internal SRAM
values are preserved throughout Power-down mode and the logic levels of chip
output pins remain static. The Power-down mode can be terminated and normal
operation resumed by either a Reset or certain specific interrupts that are able to
function without clocks. Since all dynamic operation of the chip is suspended,
Power-down mode reduces chip power consumption to nearly zero.
A Power Control for Peripherals feature allows individual peripherals to be turned off if
they are not needed in the application, resulting in additional power savings.
The VPB Divider determines the relationship between the processor clock (cclk) and
the clock used by peripheral devices (PCLK). The VPB Divider serves two purposes.
The first is that the VPB bus cannot operate at the highest speeds of the CPU. In
order to compensate for this, the VPB bus may be slowed down to one half or one
Rev. 01 — 06 February 2004
Single-chip 16/32-bit microcontrollers
DD
ramp (in the case of power on),
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
LPC2194
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